1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_MP 13 #define CONFIG_SYS_FSL_CLK 14 #define CONFIG_GICV2 15 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 21 #define CONFIG_SUPPORT_RAW_INITRD 22 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #define CONFIG_BOARD_EARLY_INIT_F 1 25 26 #define CONFIG_VERY_BIG_RAM 27 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 29 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 30 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 31 32 #define CPU_RELEASE_ADDR secondary_boot_func 33 34 /* Generic Timer Definitions */ 35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 36 37 /* Size of malloc() pool */ 38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 39 40 /* Serial Port */ 41 #define CONFIG_CONS_INDEX 1 42 #define CONFIG_SYS_NS16550_SERIAL 43 #define CONFIG_SYS_NS16550_REG_SIZE 1 44 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 45 46 #define CONFIG_BAUDRATE 115200 47 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 48 49 /* SD boot SPL */ 50 #ifdef CONFIG_SD_BOOT 51 #define CONFIG_SPL_FRAMEWORK 52 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 53 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 54 #define CONFIG_SPL_LIBCOMMON_SUPPORT 55 #define CONFIG_SPL_LIBGENERIC_SUPPORT 56 #define CONFIG_SPL_ENV_SUPPORT 57 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 58 #define CONFIG_SPL_WATCHDOG_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT 60 #define CONFIG_SPL_SERIAL_SUPPORT 61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 62 63 #define CONFIG_SPL_MMC_SUPPORT 64 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 65 #define CONFIG_SPL_TEXT_BASE 0x10000000 66 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 67 #define CONFIG_SPL_STACK 0x10020000 68 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 69 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 70 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 72 CONFIG_SPL_BSS_MAX_SIZE) 73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 74 #define CONFIG_SYS_MONITOR_LEN 0xa0000 75 #endif 76 77 /* NAND SPL */ 78 #ifdef CONFIG_NAND_BOOT 79 #define CONFIG_SPL_PBL_PAD 80 #define CONFIG_SPL_FRAMEWORK 81 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 82 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 83 #define CONFIG_SPL_LIBCOMMON_SUPPORT 84 #define CONFIG_SPL_LIBGENERIC_SUPPORT 85 #define CONFIG_SPL_ENV_SUPPORT 86 #define CONFIG_SPL_WATCHDOG_SUPPORT 87 #define CONFIG_SPL_I2C_SUPPORT 88 #define CONFIG_SPL_SERIAL_SUPPORT 89 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 90 91 #define CONFIG_SPL_NAND_SUPPORT 92 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 93 #define CONFIG_SPL_TEXT_BASE 0x10000000 94 #define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ 95 #define CONFIG_SPL_STACK 0x1001f000 96 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 98 99 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 100 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 101 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 102 CONFIG_SPL_BSS_MAX_SIZE) 103 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 104 #define CONFIG_SYS_MONITOR_LEN 0xa0000 105 #endif 106 107 /* I2C */ 108 #define CONFIG_SYS_I2C 109 #define CONFIG_SYS_I2C_MXC 110 #define CONFIG_SYS_I2C_MXC_I2C1 111 #define CONFIG_SYS_I2C_MXC_I2C2 112 #define CONFIG_SYS_I2C_MXC_I2C3 113 #define CONFIG_SYS_I2C_MXC_I2C4 114 115 /* Command line configuration */ 116 #define CONFIG_CMD_ENV 117 118 /* MMC */ 119 #define CONFIG_MMC 120 #ifdef CONFIG_MMC 121 #define CONFIG_FSL_ESDHC 122 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 123 #define CONFIG_GENERIC_MMC 124 #define CONFIG_DOS_PARTITION 125 #endif 126 127 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 128 129 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 130 131 /* FMan ucode */ 132 #define CONFIG_SYS_DPAA_FMAN 133 #ifdef CONFIG_SYS_DPAA_FMAN 134 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 135 136 #ifdef CONFIG_SD_BOOT 137 /* 138 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 139 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 140 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 141 */ 142 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 143 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 144 #elif defined(CONFIG_QSPI_BOOT) 145 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 146 #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 1000000 150 #define CONFIG_ENV_SPI_MODE 0x03 151 #elif defined(CONFIG_NAND_BOOT) 152 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 153 #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 154 #else 155 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 156 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 157 #endif 158 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 159 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 160 #endif 161 162 /* Miscellaneous configurable options */ 163 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 164 #define CONFIG_ARCH_EARLY_INIT_R 165 #define CONFIG_BOARD_LATE_INIT 166 167 #define CONFIG_HWCONFIG 168 #define HWCONFIG_BUFFER_SIZE 128 169 170 /* Initial environment variables */ 171 #define CONFIG_EXTRA_ENV_SETTINGS \ 172 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 173 "loadaddr=0x80100000\0" \ 174 "ramdisk_addr=0x800000\0" \ 175 "ramdisk_size=0x2000000\0" \ 176 "fdt_high=0xffffffffffffffff\0" \ 177 "initrd_high=0xffffffffffffffff\0" \ 178 "kernel_start=0x1000000\0" \ 179 "kernel_load=0xa0000000\0" \ 180 "kernel_size=0x2800000\0" \ 181 "console=ttyS0,115200\0" \ 182 MTDPARTS_DEFAULT "\0" 183 184 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 185 "earlycon=uart8250,mmio,0x21c0500 " \ 186 MTDPARTS_DEFAULT 187 /* Monitor Command Prompt */ 188 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 190 sizeof(CONFIG_SYS_PROMPT) + 16) 191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 192 #define CONFIG_SYS_LONGHELP 193 #define CONFIG_CMDLINE_EDITING 1 194 #define CONFIG_AUTO_COMPLETE 195 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 196 197 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 198 199 /* Hash command with SHA acceleration supported in hardware */ 200 #ifdef CONFIG_FSL_CAAM 201 #define CONFIG_CMD_HASH 202 #define CONFIG_SHA_HW_ACCEL 203 #endif 204 205 #endif /* __LS1046A_COMMON_H */ 206