1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH2 13 #define CONFIG_LS1046A 14 #define CONFIG_MP 15 #define CONFIG_SYS_FSL_CLK 16 #define CONFIG_GICV2 17 18 #include <asm/arch/config.h> 19 #ifdef CONFIG_SYS_FSL_SRDS_1 20 #define CONFIG_SYS_HAS_SERDES 21 #endif 22 23 /* Link Definitions */ 24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 25 26 #define CONFIG_SUPPORT_RAW_INITRD 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_BOARD_EARLY_INIT_F 1 30 31 #define CONFIG_VERY_BIG_RAM 32 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 33 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 34 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 35 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 36 37 #define CPU_RELEASE_ADDR secondary_boot_func 38 39 /* Generic Timer Definitions */ 40 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 41 42 /* Size of malloc() pool */ 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 44 45 /* Serial Port */ 46 #define CONFIG_CONS_INDEX 1 47 #define CONFIG_SYS_NS16550_SERIAL 48 #define CONFIG_SYS_NS16550_REG_SIZE 1 49 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 50 51 #define CONFIG_BAUDRATE 115200 52 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 53 54 /* SD boot SPL */ 55 #ifdef CONFIG_SD_BOOT 56 #define CONFIG_SPL_FRAMEWORK 57 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SPL_LIBCOMMON_SUPPORT 60 #define CONFIG_SPL_LIBGENERIC_SUPPORT 61 #define CONFIG_SPL_ENV_SUPPORT 62 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 63 #define CONFIG_SPL_WATCHDOG_SUPPORT 64 #define CONFIG_SPL_I2C_SUPPORT 65 #define CONFIG_SPL_SERIAL_SUPPORT 66 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 67 68 #define CONFIG_SPL_MMC_SUPPORT 69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x110 70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 71 #define CONFIG_SPL_TEXT_BASE 0x10000000 72 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 73 #define CONFIG_SPL_STACK 0x10020000 74 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 76 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 77 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 78 CONFIG_SPL_BSS_MAX_SIZE) 79 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 80 #define CONFIG_SYS_MONITOR_LEN 0xa0000 81 #endif 82 83 /* NAND SPL */ 84 #ifdef CONFIG_NAND_BOOT 85 #define CONFIG_SPL_PBL_PAD 86 #define CONFIG_SPL_FRAMEWORK 87 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 89 #define CONFIG_SPL_LIBCOMMON_SUPPORT 90 #define CONFIG_SPL_LIBGENERIC_SUPPORT 91 #define CONFIG_SPL_ENV_SUPPORT 92 #define CONFIG_SPL_WATCHDOG_SUPPORT 93 #define CONFIG_SPL_I2C_SUPPORT 94 #define CONFIG_SPL_SERIAL_SUPPORT 95 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 96 97 #define CONFIG_SPL_NAND_SUPPORT 98 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 99 #define CONFIG_SPL_TEXT_BASE 0x10000000 100 #define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ 101 #define CONFIG_SPL_STACK 0x1001f000 102 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 104 105 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 106 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 107 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 108 CONFIG_SPL_BSS_MAX_SIZE) 109 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 110 #define CONFIG_SYS_MONITOR_LEN 0xa0000 111 #endif 112 113 /* I2C */ 114 #define CONFIG_SYS_I2C 115 #define CONFIG_SYS_I2C_MXC 116 #define CONFIG_SYS_I2C_MXC_I2C1 117 #define CONFIG_SYS_I2C_MXC_I2C2 118 #define CONFIG_SYS_I2C_MXC_I2C3 119 #define CONFIG_SYS_I2C_MXC_I2C4 120 121 /* Command line configuration */ 122 #define CONFIG_CMD_ENV 123 124 /* MMC */ 125 #define CONFIG_MMC 126 #ifdef CONFIG_MMC 127 #define CONFIG_FSL_ESDHC 128 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 129 #define CONFIG_GENERIC_MMC 130 #define CONFIG_DOS_PARTITION 131 #endif 132 133 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 134 135 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 136 137 /* FMan ucode */ 138 #define CONFIG_SYS_DPAA_FMAN 139 #ifdef CONFIG_SYS_DPAA_FMAN 140 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 141 142 #ifdef CONFIG_SD_BOOT 143 /* 144 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 145 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 146 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 147 */ 148 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 149 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 150 #elif defined(CONFIG_QSPI_BOOT) 151 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 152 #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 153 #define CONFIG_ENV_SPI_BUS 0 154 #define CONFIG_ENV_SPI_CS 0 155 #define CONFIG_ENV_SPI_MAX_HZ 1000000 156 #define CONFIG_ENV_SPI_MODE 0x03 157 #elif defined(CONFIG_NAND_BOOT) 158 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 159 #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 160 #else 161 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 162 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 163 #endif 164 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 165 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 166 #endif 167 168 /* Miscellaneous configurable options */ 169 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 170 #define CONFIG_ARCH_EARLY_INIT_R 171 #define CONFIG_BOARD_LATE_INIT 172 173 #define CONFIG_HWCONFIG 174 #define HWCONFIG_BUFFER_SIZE 128 175 176 /* Initial environment variables */ 177 #define CONFIG_EXTRA_ENV_SETTINGS \ 178 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 179 "loadaddr=0x80100000\0" \ 180 "ramdisk_addr=0x800000\0" \ 181 "ramdisk_size=0x2000000\0" \ 182 "fdt_high=0xffffffffffffffff\0" \ 183 "initrd_high=0xffffffffffffffff\0" \ 184 "kernel_start=0x1000000\0" \ 185 "kernel_load=0xa0000000\0" \ 186 "kernel_size=0x2800000\0" \ 187 "console=ttyS0,115200\0" \ 188 MTDPARTS_DEFAULT "\0" 189 190 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 191 "earlycon=uart8250,mmio,0x21c0500 " \ 192 MTDPARTS_DEFAULT 193 /* Monitor Command Prompt */ 194 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 195 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 196 sizeof(CONFIG_SYS_PROMPT) + 16) 197 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 198 #define CONFIG_SYS_LONGHELP 199 #define CONFIG_CMDLINE_EDITING 1 200 #define CONFIG_AUTO_COMPLETE 201 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 202 203 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 204 205 /* Hash command with SHA acceleration supported in hardware */ 206 #ifdef CONFIG_FSL_CAAM 207 #define CONFIG_CMD_HASH 208 #define CONFIG_SHA_HW_ACCEL 209 #endif 210 211 #endif /* __LS1046A_COMMON_H */ 212