xref: /rk3399_rockchip-uboot/include/configs/ls1046a_common.h (revision f7b75f8b34a40b2d13e968d52bb2e8ae271401c9)
1dd02936fSMingkai Hu /*
2dd02936fSMingkai Hu  * Copyright 2016 Freescale Semiconductor
3dd02936fSMingkai Hu  *
4dd02936fSMingkai Hu  * SPDX-License-Identifier:	GPL-2.0+
5dd02936fSMingkai Hu  */
6dd02936fSMingkai Hu 
7dd02936fSMingkai Hu #ifndef __LS1046A_COMMON_H
8dd02936fSMingkai Hu #define __LS1046A_COMMON_H
9dd02936fSMingkai Hu 
10a52ff334SSumit Garg /* SPL build */
11a52ff334SSumit Garg #ifdef CONFIG_SPL_BUILD
12a52ff334SSumit Garg #define SPL_NO_QBMAN
13a52ff334SSumit Garg #define SPL_NO_FMAN
14a52ff334SSumit Garg #define SPL_NO_ENV
15a52ff334SSumit Garg #define SPL_NO_MISC
16a52ff334SSumit Garg #define SPL_NO_QSPI
17a52ff334SSumit Garg #define SPL_NO_USB
18a52ff334SSumit Garg #define SPL_NO_SATA
19a52ff334SSumit Garg #endif
20a52ff334SSumit Garg #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
21a52ff334SSumit Garg #define SPL_NO_MMC
22a52ff334SSumit Garg #endif
23a52ff334SSumit Garg #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
24a52ff334SSumit Garg #define SPL_NO_IFC
25a52ff334SSumit Garg #endif
26a52ff334SSumit Garg 
27dd02936fSMingkai Hu #define CONFIG_REMAKE_ELF
28dd02936fSMingkai Hu #define CONFIG_FSL_LAYERSCAPE
29dd02936fSMingkai Hu #define CONFIG_MP
30dd02936fSMingkai Hu #define CONFIG_GICV2
31dd02936fSMingkai Hu 
32dd02936fSMingkai Hu #include <asm/arch/config.h>
33b52a0507SBharat Bhushan #include <asm/arch/stream_id_lsch2.h>
34dd02936fSMingkai Hu 
35dd02936fSMingkai Hu /* Link Definitions */
36dd02936fSMingkai Hu #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37dd02936fSMingkai Hu 
38dd02936fSMingkai Hu #define CONFIG_SUPPORT_RAW_INITRD
39dd02936fSMingkai Hu 
40dd02936fSMingkai Hu #define CONFIG_SKIP_LOWLEVEL_INIT
41dd02936fSMingkai Hu 
42dd02936fSMingkai Hu #define CONFIG_VERY_BIG_RAM
43dd02936fSMingkai Hu #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
44dd02936fSMingkai Hu #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
45dd02936fSMingkai Hu #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
46dd02936fSMingkai Hu #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
47dd02936fSMingkai Hu 
48dd02936fSMingkai Hu #define CPU_RELEASE_ADDR               secondary_boot_func
49dd02936fSMingkai Hu 
50dd02936fSMingkai Hu /* Generic Timer Definitions */
51dd02936fSMingkai Hu #define COUNTER_FREQUENCY		25000000	/* 25MHz */
52dd02936fSMingkai Hu 
53dd02936fSMingkai Hu /* Size of malloc() pool */
54dd02936fSMingkai Hu #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
55dd02936fSMingkai Hu 
56dd02936fSMingkai Hu /* Serial Port */
57dd02936fSMingkai Hu #define CONFIG_CONS_INDEX		1
58dd02936fSMingkai Hu #define CONFIG_SYS_NS16550_SERIAL
59dd02936fSMingkai Hu #define CONFIG_SYS_NS16550_REG_SIZE	1
60904110c7SHou Zhiqiang #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
61dd02936fSMingkai Hu 
62dd02936fSMingkai Hu #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
63dd02936fSMingkai Hu 
64dd02936fSMingkai Hu /* SD boot SPL */
65dd02936fSMingkai Hu #ifdef CONFIG_SD_BOOT
66dd02936fSMingkai Hu #define CONFIG_SPL_FRAMEWORK
67dd02936fSMingkai Hu #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
68dd02936fSMingkai Hu #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
69dd02936fSMingkai Hu #define CONFIG_SPL_LIBCOMMON_SUPPORT
70dd02936fSMingkai Hu #define CONFIG_SPL_LIBGENERIC_SUPPORT
71dd02936fSMingkai Hu #define CONFIG_SPL_ENV_SUPPORT
72dd02936fSMingkai Hu #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
73dd02936fSMingkai Hu #define CONFIG_SPL_WATCHDOG_SUPPORT
74dd02936fSMingkai Hu #define CONFIG_SPL_I2C_SUPPORT
75dd02936fSMingkai Hu #define CONFIG_SPL_SERIAL_SUPPORT
76dd02936fSMingkai Hu #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
77dd02936fSMingkai Hu 
78dd02936fSMingkai Hu #define CONFIG_SPL_MMC_SUPPORT
79dd02936fSMingkai Hu #define CONFIG_SPL_TEXT_BASE		0x10000000
80dd02936fSMingkai Hu #define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
81dd02936fSMingkai Hu #define CONFIG_SPL_STACK		0x10020000
82dd02936fSMingkai Hu #define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
83dd02936fSMingkai Hu #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
84dd02936fSMingkai Hu #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
85dd02936fSMingkai Hu #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
86dd02936fSMingkai Hu 					CONFIG_SPL_BSS_MAX_SIZE)
87dd02936fSMingkai Hu #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
88511fc86dSRuchika Gupta 
89511fc86dSRuchika Gupta #ifdef CONFIG_SECURE_BOOT
90511fc86dSRuchika Gupta #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
91511fc86dSRuchika Gupta /*
92511fc86dSRuchika Gupta  * HDR would be appended at end of image and copied to DDR along
93511fc86dSRuchika Gupta  * with U-Boot image. Here u-boot max. size is 512K. So if binary
94511fc86dSRuchika Gupta  * size increases then increase this size in case of secure boot as
95511fc86dSRuchika Gupta  * it uses raw u-boot image instead of fit image.
96511fc86dSRuchika Gupta  */
97511fc86dSRuchika Gupta #define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
98511fc86dSRuchika Gupta #else
99511fc86dSRuchika Gupta #define CONFIG_SYS_MONITOR_LEN		0x100000
100511fc86dSRuchika Gupta #endif /* ifdef CONFIG_SECURE_BOOT */
101dd02936fSMingkai Hu #endif
102dd02936fSMingkai Hu 
103126fe70dSShaohui Xie /* NAND SPL */
104126fe70dSShaohui Xie #ifdef CONFIG_NAND_BOOT
105126fe70dSShaohui Xie #define CONFIG_SPL_PBL_PAD
106126fe70dSShaohui Xie #define CONFIG_SPL_FRAMEWORK
107126fe70dSShaohui Xie #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
108126fe70dSShaohui Xie #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
109126fe70dSShaohui Xie #define CONFIG_SPL_LIBCOMMON_SUPPORT
110126fe70dSShaohui Xie #define CONFIG_SPL_LIBGENERIC_SUPPORT
111126fe70dSShaohui Xie #define CONFIG_SPL_ENV_SUPPORT
112126fe70dSShaohui Xie #define CONFIG_SPL_WATCHDOG_SUPPORT
113126fe70dSShaohui Xie #define CONFIG_SPL_I2C_SUPPORT
114126fe70dSShaohui Xie #define CONFIG_SPL_SERIAL_SUPPORT
115126fe70dSShaohui Xie #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
116126fe70dSShaohui Xie 
117126fe70dSShaohui Xie #define CONFIG_SPL_NAND_SUPPORT
118126fe70dSShaohui Xie #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
119126fe70dSShaohui Xie #define CONFIG_SPL_TEXT_BASE		0x10000000
120511fc86dSRuchika Gupta #define CONFIG_SPL_MAX_SIZE		0x17000		/* 90 KiB */
121126fe70dSShaohui Xie #define CONFIG_SPL_STACK		0x1001f000
122126fe70dSShaohui Xie #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
123126fe70dSShaohui Xie #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
124126fe70dSShaohui Xie 
125126fe70dSShaohui Xie #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
126126fe70dSShaohui Xie #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
127126fe70dSShaohui Xie #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
128126fe70dSShaohui Xie 					CONFIG_SPL_BSS_MAX_SIZE)
129126fe70dSShaohui Xie #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
130126fe70dSShaohui Xie #define CONFIG_SYS_MONITOR_LEN		0xa0000
131126fe70dSShaohui Xie #endif
132126fe70dSShaohui Xie 
133dd02936fSMingkai Hu /* I2C */
134dd02936fSMingkai Hu #define CONFIG_SYS_I2C
135dd02936fSMingkai Hu #define CONFIG_SYS_I2C_MXC
136dd02936fSMingkai Hu #define CONFIG_SYS_I2C_MXC_I2C1
137dd02936fSMingkai Hu #define CONFIG_SYS_I2C_MXC_I2C2
138dd02936fSMingkai Hu #define CONFIG_SYS_I2C_MXC_I2C3
139dd02936fSMingkai Hu #define CONFIG_SYS_I2C_MXC_I2C4
140dd02936fSMingkai Hu 
1413098e539SHou Zhiqiang /* PCIe */
1423098e539SHou Zhiqiang #define CONFIG_PCIE1		/* PCIE controller 1 */
1433098e539SHou Zhiqiang #define CONFIG_PCIE2		/* PCIE controller 2 */
1443098e539SHou Zhiqiang #define CONFIG_PCIE3		/* PCIE controller 3 */
1453098e539SHou Zhiqiang 
1463098e539SHou Zhiqiang #ifdef CONFIG_PCI
1473098e539SHou Zhiqiang #define CONFIG_PCI_SCAN_SHOW
1483098e539SHou Zhiqiang #define CONFIG_CMD_PCI
1493098e539SHou Zhiqiang #endif
1503098e539SHou Zhiqiang 
151dd02936fSMingkai Hu /* Command line configuration */
152dd02936fSMingkai Hu 
153dd02936fSMingkai Hu /* MMC */
154a52ff334SSumit Garg #ifndef SPL_NO_MMC
155dd02936fSMingkai Hu #ifdef CONFIG_MMC
156dd02936fSMingkai Hu #define CONFIG_FSL_ESDHC
157dd02936fSMingkai Hu #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
158dd02936fSMingkai Hu #endif
159a52ff334SSumit Garg #endif
160dd02936fSMingkai Hu 
161a52ff334SSumit Garg #ifndef SPL_NO_QBMAN
162dd02936fSMingkai Hu #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
163a52ff334SSumit Garg #endif
164dd02936fSMingkai Hu 
165dd02936fSMingkai Hu /* FMan ucode */
166a52ff334SSumit Garg #ifndef SPL_NO_FMAN
167dd02936fSMingkai Hu #define CONFIG_SYS_DPAA_FMAN
168dd02936fSMingkai Hu #ifdef CONFIG_SYS_DPAA_FMAN
169dd02936fSMingkai Hu #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
170a52ff334SSumit Garg #endif
171dd02936fSMingkai Hu 
172dd02936fSMingkai Hu #ifdef CONFIG_SD_BOOT
173dd02936fSMingkai Hu /*
174dd02936fSMingkai Hu  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
175dd02936fSMingkai Hu  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
1768104deb2SAlison Wang  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
177dd02936fSMingkai Hu  */
178dd02936fSMingkai Hu #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
1798104deb2SAlison Wang #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
180126fe70dSShaohui Xie #elif defined(CONFIG_QSPI_BOOT)
181dd02936fSMingkai Hu #define CONFIG_SYS_QE_FW_IN_SPIFLASH
1828104deb2SAlison Wang #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
183dd02936fSMingkai Hu #define CONFIG_ENV_SPI_BUS		0
184dd02936fSMingkai Hu #define CONFIG_ENV_SPI_CS		0
185dd02936fSMingkai Hu #define CONFIG_ENV_SPI_MAX_HZ		1000000
186dd02936fSMingkai Hu #define CONFIG_ENV_SPI_MODE		0x03
187126fe70dSShaohui Xie #elif defined(CONFIG_NAND_BOOT)
188126fe70dSShaohui Xie #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
1898104deb2SAlison Wang #define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
190126fe70dSShaohui Xie #else
191126fe70dSShaohui Xie #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
1928104deb2SAlison Wang #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
193dd02936fSMingkai Hu #endif
194dd02936fSMingkai Hu #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
195dd02936fSMingkai Hu #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
196dd02936fSMingkai Hu #endif
197dd02936fSMingkai Hu 
198dd02936fSMingkai Hu /* Miscellaneous configurable options */
199dd02936fSMingkai Hu #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
200dd02936fSMingkai Hu 
201dd02936fSMingkai Hu #define CONFIG_HWCONFIG
202dd02936fSMingkai Hu #define HWCONFIG_BUFFER_SIZE		128
203dd02936fSMingkai Hu 
2048de227eeSQianyu Gong #include <config_distro_defaults.h>
2058de227eeSQianyu Gong #ifndef CONFIG_SPL_BUILD
2068de227eeSQianyu Gong #define BOOT_TARGET_DEVICES(func) \
2078de227eeSQianyu Gong 	func(MMC, mmc, 0) \
2088de227eeSQianyu Gong 	func(USB, usb, 0)
2098de227eeSQianyu Gong #include <config_distro_bootcmd.h>
2108de227eeSQianyu Gong #endif
2118de227eeSQianyu Gong 
212a52ff334SSumit Garg #ifndef SPL_NO_MISC
213dd02936fSMingkai Hu /* Initial environment variables */
214dd02936fSMingkai Hu #define CONFIG_EXTRA_ENV_SETTINGS		\
215dd02936fSMingkai Hu 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
216dd02936fSMingkai Hu 	"ramdisk_addr=0x800000\0"		\
217dd02936fSMingkai Hu 	"ramdisk_size=0x2000000\0"		\
218dd02936fSMingkai Hu 	"fdt_high=0xffffffffffffffff\0"		\
219dd02936fSMingkai Hu 	"initrd_high=0xffffffffffffffff\0"	\
2208de227eeSQianyu Gong 	"fdt_addr=0x64f00000\0"                 \
2218de227eeSQianyu Gong 	"kernel_addr=0x65000000\0"              \
2228de227eeSQianyu Gong 	"scriptaddr=0x80000000\0"               \
223*f7b75f8bSSumit Garg 	"scripthdraddr=0x80080000\0"		\
2248de227eeSQianyu Gong 	"fdtheader_addr_r=0x80100000\0"         \
2258de227eeSQianyu Gong 	"kernelheader_addr_r=0x80200000\0"      \
2268de227eeSQianyu Gong 	"load_addr=0xa0000000\0"            \
227*f7b75f8bSSumit Garg 	"kernel_addr_r=0x81000000\0"            \
2288de227eeSQianyu Gong 	"fdt_addr_r=0x90000000\0"               \
2298de227eeSQianyu Gong 	"ramdisk_addr_r=0xa0000000\0"           \
230dd02936fSMingkai Hu 	"kernel_start=0x1000000\0"		\
231dd02936fSMingkai Hu 	"kernel_load=0xa0000000\0"		\
232dd02936fSMingkai Hu 	"kernel_size=0x2800000\0"		\
233dd02936fSMingkai Hu 	"console=ttyS0,115200\0"                \
2348de227eeSQianyu Gong 		MTDPARTS_DEFAULT "\0"		\
2358de227eeSQianyu Gong 	BOOTENV					\
2368de227eeSQianyu Gong 	"boot_scripts=ls1046ardb_boot.scr\0"    \
237*f7b75f8bSSumit Garg 	"boot_script_hdr=hdr_ls1046ardb_bs.out\0"	\
2388de227eeSQianyu Gong 	"scan_dev_for_boot_part="               \
2398de227eeSQianyu Gong 		"part list ${devtype} ${devnum} devplist; "   \
2408de227eeSQianyu Gong 		"env exists devplist || setenv devplist 1; "  \
2418de227eeSQianyu Gong 		"for distro_bootpart in ${devplist}; do "     \
2428de227eeSQianyu Gong 		  "if fstype ${devtype} "                  \
2438de227eeSQianyu Gong 			"${devnum}:${distro_bootpart} "      \
2448de227eeSQianyu Gong 			"bootfstype; then "                  \
2458de227eeSQianyu Gong 			"run scan_dev_for_boot; "            \
2468de227eeSQianyu Gong 		  "fi; "                                   \
2478de227eeSQianyu Gong 		"done\0"                                   \
248*f7b75f8bSSumit Garg 	"scan_dev_for_boot="				  \
249*f7b75f8bSSumit Garg 		"echo Scanning ${devtype} "		  \
250*f7b75f8bSSumit Garg 				"${devnum}:${distro_bootpart}...; "  \
251*f7b75f8bSSumit Garg 		"for prefix in ${boot_prefixes}; do "	  \
252*f7b75f8bSSumit Garg 			"run scan_dev_for_scripts; "	  \
253*f7b75f8bSSumit Garg 		"done;"					  \
254*f7b75f8bSSumit Garg 		"\0"					  \
255*f7b75f8bSSumit Garg 	"boot_a_script="				  \
256*f7b75f8bSSumit Garg 		"load ${devtype} ${devnum}:${distro_bootpart} "  \
257*f7b75f8bSSumit Garg 			"${scriptaddr} ${prefix}${script}; "    \
258*f7b75f8bSSumit Garg 		"env exists secureboot && load ${devtype} "     \
259*f7b75f8bSSumit Garg 			"${devnum}:${distro_bootpart} "		\
260*f7b75f8bSSumit Garg 			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
261*f7b75f8bSSumit Garg 			"&& esbc_validate ${scripthdraddr};"    \
262*f7b75f8bSSumit Garg 		"source ${scriptaddr}\0"	  \
2638de227eeSQianyu Gong 	"installer=load mmc 0:2 $load_addr "          \
2648de227eeSQianyu Gong 		"/flex_installer_arm64.itb; "          \
2658de227eeSQianyu Gong 		"bootm $load_addr#ls1046ardb\0"	 \
2668de227eeSQianyu Gong 	"qspi_bootcmd=echo Trying load from qspi..;"      \
2678de227eeSQianyu Gong 		"sf probe && sf read $load_addr "         \
2688de227eeSQianyu Gong 		"$kernel_start $kernel_size && bootm $load_addr#$board\0"
2698de227eeSQianyu Gong 
270dd02936fSMingkai Hu 
271dd02936fSMingkai Hu #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
272dd02936fSMingkai Hu 					"earlycon=uart8250,mmio,0x21c0500 " \
273dd02936fSMingkai Hu 					MTDPARTS_DEFAULT
274a52ff334SSumit Garg #endif
275a52ff334SSumit Garg 
276dd02936fSMingkai Hu /* Monitor Command Prompt */
277dd02936fSMingkai Hu #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
278dd02936fSMingkai Hu #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
279dd02936fSMingkai Hu 					sizeof(CONFIG_SYS_PROMPT) + 16)
280dd02936fSMingkai Hu #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
281dd02936fSMingkai Hu #define CONFIG_SYS_LONGHELP
282a52ff334SSumit Garg 
283dd02936fSMingkai Hu #define CONFIG_AUTO_COMPLETE
284dd02936fSMingkai Hu #define CONFIG_SYS_MAXARGS		64	/* max command args */
285dd02936fSMingkai Hu 
286dd02936fSMingkai Hu #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
287dd02936fSMingkai Hu 
288457e51cfSSimon Glass #include <asm/arch/soc.h>
289457e51cfSSimon Glass 
290dd02936fSMingkai Hu #endif /* __LS1046A_COMMON_H */
291