1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043ARDB_H__ 8 #define __LS1043ARDB_H__ 9 10 #include "ls1043a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_NAND_BOOT) 16 #define CONFIG_SYS_TEXT_BASE 0x82000000 17 #else 18 #define CONFIG_SYS_TEXT_BASE 0x60100000 19 #endif 20 21 #define CONFIG_SYS_CLK_FREQ 100000000 22 #define CONFIG_DDR_CLK_FREQ 100000000 23 24 #define CONFIG_LAYERSCAPE_NS_ACCESS 25 #define CONFIG_MISC_INIT_R 26 27 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 28 /* Physical Memory Map */ 29 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 30 #define CONFIG_NR_DRAM_BANKS 1 31 32 #define CONFIG_SYS_SPD_BUS_NUM 0 33 34 #define CONFIG_FSL_DDR_BIST 35 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 36 #define CONFIG_SYS_DDR_RAW_TIMING 37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 40 #ifdef CONFIG_RAMBOOT_PBL 41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 42 #endif 43 44 #ifdef CONFIG_NAND_BOOT 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 46 #endif 47 48 /* 49 * NOR Flash Definitions 50 */ 51 #define CONFIG_SYS_NOR_CSPR_EXT (0x0) 52 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 53 #define CONFIG_SYS_NOR_CSPR \ 54 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 55 CSPR_PORT_SIZE_16 | \ 56 CSPR_MSEL_NOR | \ 57 CSPR_V) 58 59 /* NOR Flash Timing Params */ 60 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 61 CSOR_NOR_TRHZ_80) 62 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 63 FTIM0_NOR_TEADC(0x1) | \ 64 FTIM0_NOR_TAVDS(0x0) | \ 65 FTIM0_NOR_TEAHC(0xc)) 66 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 67 FTIM1_NOR_TRAD_NOR(0xb) | \ 68 FTIM1_NOR_TSEQRAD_NOR(0x9)) 69 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 70 FTIM2_NOR_TCH(0x4) | \ 71 FTIM2_NOR_TWPH(0x8) | \ 72 FTIM2_NOR_TWP(0x10)) 73 #define CONFIG_SYS_NOR_FTIM3 0 74 #define CONFIG_SYS_IFC_CCR 0x01000000 75 76 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 77 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 78 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 79 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 80 81 #define CONFIG_SYS_FLASH_EMPTY_INFO 82 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 83 84 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 85 #define CONFIG_SYS_WRITE_SWAPPED_DATA 86 87 /* 88 * NAND Flash Definitions 89 */ 90 #define CONFIG_NAND_FSL_IFC 91 92 #define CONFIG_SYS_NAND_BASE 0x7e800000 93 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 94 95 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 96 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 97 | CSPR_PORT_SIZE_8 \ 98 | CSPR_MSEL_NAND \ 99 | CSPR_V) 100 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 101 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 102 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 103 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 104 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 105 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 106 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 107 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 108 109 #define CONFIG_SYS_NAND_ONFI_DETECTION 110 111 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 112 FTIM0_NAND_TWP(0x18) | \ 113 FTIM0_NAND_TWCHT(0x7) | \ 114 FTIM0_NAND_TWH(0xa)) 115 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 116 FTIM1_NAND_TWBE(0x39) | \ 117 FTIM1_NAND_TRR(0xe) | \ 118 FTIM1_NAND_TRP(0x18)) 119 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 120 FTIM2_NAND_TREH(0xa) | \ 121 FTIM2_NAND_TWHRE(0x1e)) 122 #define CONFIG_SYS_NAND_FTIM3 0x0 123 124 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 126 #define CONFIG_MTD_NAND_VERIFY_WRITE 127 #define CONFIG_CMD_NAND 128 129 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 130 131 #ifdef CONFIG_NAND_BOOT 132 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 133 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 134 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 135 #endif 136 137 /* 138 * CPLD 139 */ 140 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 141 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 142 143 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 144 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 145 CSPR_PORT_SIZE_8 | \ 146 CSPR_MSEL_GPCM | \ 147 CSPR_V) 148 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 149 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 150 CSOR_NOR_NOR_MODE_AVD_NOR | \ 151 CSOR_NOR_TRHZ_80) 152 153 /* CPLD Timing parameters for IFC GPCM */ 154 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 155 FTIM0_GPCM_TEADC(0xf) | \ 156 FTIM0_GPCM_TEAHC(0xf)) 157 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 158 FTIM1_GPCM_TRAD(0x3f)) 159 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 160 FTIM2_GPCM_TCH(0xf) | \ 161 FTIM2_GPCM_TWP(0xff)) 162 #define CONFIG_SYS_CPLD_FTIM3 0x0 163 164 /* IFC Timing Params */ 165 #ifdef CONFIG_NAND_BOOT 166 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 167 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 168 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 169 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 170 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 171 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 172 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 173 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 174 175 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 176 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 177 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 178 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 179 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 180 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 181 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 182 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 183 #else 184 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 185 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 186 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 187 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 188 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 189 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 190 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 191 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 192 193 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 194 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 195 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 196 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 197 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 198 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 199 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 200 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 201 #endif 202 203 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 204 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 205 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 206 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 207 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 208 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 209 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 210 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 211 212 /* EEPROM */ 213 #define CONFIG_ID_EEPROM 214 #define CONFIG_SYS_I2C_EEPROM_NXID 215 #define CONFIG_SYS_EEPROM_BUS_NUM 0 216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 220 221 /* 222 * Environment 223 */ 224 #define CONFIG_ENV_OVERWRITE 225 226 #if defined(CONFIG_NAND_BOOT) 227 #define CONFIG_ENV_IS_IN_NAND 228 #define CONFIG_ENV_SIZE 0x2000 229 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 230 #else 231 #define CONFIG_ENV_IS_IN_FLASH 232 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 233 #define CONFIG_ENV_SECT_SIZE 0x20000 234 #define CONFIG_ENV_SIZE 0x20000 235 #endif 236 237 #endif /* __LS1043ARDB_H__ */ 238