1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40010000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 42 43 #define CONFIG_DDR_ECC 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 #ifdef CONFIG_SYS_DPAA_FMAN 50 #define CONFIG_FMAN_ENET 51 #define CONFIG_PHYLIB 52 #define CONFIG_PHY_VITESSE 53 #define CONFIG_PHY_REALTEK 54 #define CONFIG_PHYLIB_10G 55 #define RGMII_PHY1_ADDR 0x1 56 #define RGMII_PHY2_ADDR 0x2 57 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 58 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 59 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 60 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 61 /* PHY address on QSGMII riser card on slot 1 */ 62 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 63 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 64 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 65 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 66 /* PHY address on QSGMII riser card on slot 2 */ 67 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 68 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 69 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 70 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 71 #endif 72 73 #ifdef CONFIG_RAMBOOT_PBL 74 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 75 #endif 76 77 #ifdef CONFIG_NAND_BOOT 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 79 #endif 80 81 #ifdef CONFIG_SD_BOOT 82 #ifdef CONFIG_SD_BOOT_QSPI 83 #define CONFIG_SYS_FSL_PBL_RCW \ 84 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 85 #else 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 87 #endif 88 #endif 89 90 /* LPUART */ 91 #ifdef CONFIG_LPUART 92 #define CONFIG_LPUART_32B_REG 93 #endif 94 95 /* SATA */ 96 #define CONFIG_LIBATA 97 #define CONFIG_SCSI_AHCI 98 #define CONFIG_SCSI_AHCI_PLAT 99 #define CONFIG_SCSI 100 101 #define CONFIG_PARTITION_UUIDS 102 #define CONFIG_EFI_PARTITION 103 #define CONFIG_CMD_GPT 104 105 /* EEPROM */ 106 #define CONFIG_ID_EEPROM 107 #define CONFIG_SYS_I2C_EEPROM_NXID 108 #define CONFIG_SYS_EEPROM_BUS_NUM 0 109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 113 114 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 115 116 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 117 #define CONFIG_SYS_SCSI_MAX_LUN 1 118 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 119 CONFIG_SYS_SCSI_MAX_LUN) 120 121 /* 122 * IFC Definitions 123 */ 124 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 125 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 126 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 127 CSPR_PORT_SIZE_16 | \ 128 CSPR_MSEL_NOR | \ 129 CSPR_V) 130 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 131 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 132 + 0x8000000) | \ 133 CSPR_PORT_SIZE_16 | \ 134 CSPR_MSEL_NOR | \ 135 CSPR_V) 136 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 137 138 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 139 CSOR_NOR_TRHZ_80) 140 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 141 FTIM0_NOR_TEADC(0x5) | \ 142 FTIM0_NOR_TEAHC(0x5)) 143 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 144 FTIM1_NOR_TRAD_NOR(0x1a) | \ 145 FTIM1_NOR_TSEQRAD_NOR(0x13)) 146 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 147 FTIM2_NOR_TCH(0x4) | \ 148 FTIM2_NOR_TWPH(0xe) | \ 149 FTIM2_NOR_TWP(0x1c)) 150 #define CONFIG_SYS_NOR_FTIM3 0 151 152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 153 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 156 157 #define CONFIG_SYS_FLASH_EMPTY_INFO 158 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 159 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 160 161 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 162 #define CONFIG_SYS_WRITE_SWAPPED_DATA 163 164 /* 165 * NAND Flash Definitions 166 */ 167 #define CONFIG_NAND_FSL_IFC 168 169 #define CONFIG_SYS_NAND_BASE 0x7e800000 170 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 171 172 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 173 174 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 175 | CSPR_PORT_SIZE_8 \ 176 | CSPR_MSEL_NAND \ 177 | CSPR_V) 178 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 179 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 180 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 181 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 182 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 183 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 184 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 185 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 186 187 #define CONFIG_SYS_NAND_ONFI_DETECTION 188 189 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 190 FTIM0_NAND_TWP(0x18) | \ 191 FTIM0_NAND_TWCHT(0x7) | \ 192 FTIM0_NAND_TWH(0xa)) 193 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 194 FTIM1_NAND_TWBE(0x39) | \ 195 FTIM1_NAND_TRR(0xe) | \ 196 FTIM1_NAND_TRP(0x18)) 197 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 198 FTIM2_NAND_TREH(0xa) | \ 199 FTIM2_NAND_TWHRE(0x1e)) 200 #define CONFIG_SYS_NAND_FTIM3 0x0 201 202 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 203 #define CONFIG_SYS_MAX_NAND_DEVICE 1 204 #define CONFIG_MTD_NAND_VERIFY_WRITE 205 #define CONFIG_CMD_NAND 206 207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 208 #endif 209 210 #ifdef CONFIG_NAND_BOOT 211 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 212 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 213 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 214 #endif 215 216 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 217 #define CONFIG_QIXIS_I2C_ACCESS 218 #define CONFIG_SYS_I2C_EARLY_INIT 219 #define CONFIG_SYS_NO_FLASH 220 #endif 221 222 /* 223 * QIXIS Definitions 224 */ 225 #define CONFIG_FSL_QIXIS 226 227 #ifdef CONFIG_FSL_QIXIS 228 #define QIXIS_BASE 0x7fb00000 229 #define QIXIS_BASE_PHYS QIXIS_BASE 230 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 231 #define QIXIS_LBMAP_SWITCH 6 232 #define QIXIS_LBMAP_MASK 0x0f 233 #define QIXIS_LBMAP_SHIFT 0 234 #define QIXIS_LBMAP_DFLTBANK 0x00 235 #define QIXIS_LBMAP_ALTBANK 0x04 236 #define QIXIS_LBMAP_NAND 0x09 237 #define QIXIS_LBMAP_SD 0x00 238 #define QIXIS_LBMAP_SD_QSPI 0xff 239 #define QIXIS_LBMAP_QSPI 0xff 240 #define QIXIS_RCW_SRC_NAND 0x106 241 #define QIXIS_RCW_SRC_SD 0x040 242 #define QIXIS_RCW_SRC_QSPI 0x045 243 #define QIXIS_RST_CTL_RESET 0x41 244 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 245 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 246 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 247 248 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 249 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 250 CSPR_PORT_SIZE_8 | \ 251 CSPR_MSEL_GPCM | \ 252 CSPR_V) 253 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 254 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 255 CSOR_NOR_NOR_MODE_AVD_NOR | \ 256 CSOR_NOR_TRHZ_80) 257 258 /* 259 * QIXIS Timing parameters for IFC GPCM 260 */ 261 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 262 FTIM0_GPCM_TEADC(0x20) | \ 263 FTIM0_GPCM_TEAHC(0x10)) 264 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 265 FTIM1_GPCM_TRAD(0x1f)) 266 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 267 FTIM2_GPCM_TCH(0x8) | \ 268 FTIM2_GPCM_TWP(0xf0)) 269 #define CONFIG_SYS_FPGA_FTIM3 0x0 270 #endif 271 272 #ifdef CONFIG_NAND_BOOT 273 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 274 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 275 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 276 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 277 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 278 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 279 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 280 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 281 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 282 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 283 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 284 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 285 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 286 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 287 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 288 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 289 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 290 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 291 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 292 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 293 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 294 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 295 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 296 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 297 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 298 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 299 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 300 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 301 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 302 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 303 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 304 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 305 #else 306 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 323 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 324 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 325 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 326 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 327 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 328 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 329 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 330 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 331 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 332 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 333 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 334 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 335 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 336 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 337 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 338 #endif 339 340 /* 341 * I2C bus multiplexer 342 */ 343 #define I2C_MUX_PCA_ADDR_PRI 0x77 344 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 345 #define I2C_RETIMER_ADDR 0x18 346 #define I2C_MUX_CH_DEFAULT 0x8 347 #define I2C_MUX_CH_CH7301 0xC 348 #define I2C_MUX_CH5 0xD 349 #define I2C_MUX_CH7 0xF 350 351 #define I2C_MUX_CH_VOL_MONITOR 0xa 352 353 /* Voltage monitor on channel 2*/ 354 #define I2C_VOL_MONITOR_ADDR 0x40 355 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 356 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 357 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 358 359 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 360 #ifndef CONFIG_SPL_BUILD 361 #define CONFIG_VID 362 #endif 363 #define CONFIG_VOL_MONITOR_IR36021_SET 364 #define CONFIG_VOL_MONITOR_INA220 365 /* The lowest and highest voltage allowed for LS1043AQDS */ 366 #define VDD_MV_MIN 819 367 #define VDD_MV_MAX 1212 368 369 /* QSPI device */ 370 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 371 #define CONFIG_FSL_QSPI 372 #ifdef CONFIG_FSL_QSPI 373 #define CONFIG_SPI_FLASH_SPANSION 374 #define FSL_QSPI_FLASH_SIZE (1 << 24) 375 #define FSL_QSPI_FLASH_NUM 2 376 #endif 377 #endif 378 379 /* USB */ 380 #define CONFIG_HAS_FSL_XHCI_USB 381 #ifdef CONFIG_HAS_FSL_XHCI_USB 382 #define CONFIG_USB_XHCI_FSL 383 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 384 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 385 #endif 386 387 /* 388 * Miscellaneous configurable options 389 */ 390 #define CONFIG_MISC_INIT_R 391 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 392 #define CONFIG_AUTO_COMPLETE 393 #define CONFIG_SYS_PBSIZE \ 394 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 395 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 396 397 #define CONFIG_SYS_MEMTEST_START 0x80000000 398 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 399 400 #define CONFIG_SYS_HZ 1000 401 402 /* 403 * Stack sizes 404 * The stack sizes are set up in start.S using the settings below 405 */ 406 #define CONFIG_STACKSIZE (30 * 1024) 407 408 #define CONFIG_SYS_INIT_SP_OFFSET \ 409 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 410 411 #ifdef CONFIG_SPL_BUILD 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 413 #else 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 415 #endif 416 417 /* 418 * Environment 419 */ 420 #define CONFIG_ENV_OVERWRITE 421 422 #ifdef CONFIG_NAND_BOOT 423 #define CONFIG_ENV_IS_IN_NAND 424 #define CONFIG_ENV_SIZE 0x2000 425 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 426 #elif defined(CONFIG_SD_BOOT) 427 #define CONFIG_ENV_OFFSET (1024 * 1024) 428 #define CONFIG_ENV_IS_IN_MMC 429 #define CONFIG_SYS_MMC_ENV_DEV 0 430 #define CONFIG_ENV_SIZE 0x2000 431 #elif defined(CONFIG_QSPI_BOOT) 432 #define CONFIG_ENV_IS_IN_SPI_FLASH 433 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 434 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 435 #define CONFIG_ENV_SECT_SIZE 0x10000 436 #else 437 #define CONFIG_ENV_IS_IN_FLASH 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 439 #define CONFIG_ENV_SECT_SIZE 0x20000 440 #define CONFIG_ENV_SIZE 0x20000 441 #endif 442 443 #define CONFIG_CMDLINE_TAG 444 445 #include <asm/fsl_secure_boot.h> 446 447 #endif /* __LS1043AQDS_H__ */ 448