1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH2 13 #define CONFIG_LS1043A 14 #define CONFIG_SYS_FSL_CLK 15 #define CONFIG_GICV2 16 17 #include <asm/arch/config.h> 18 #ifdef CONFIG_SYS_FSL_SRDS_1 19 #define CONFIG_SYS_HAS_SERDES 20 #endif 21 22 /* Link Definitions */ 23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 24 25 #define CONFIG_SUPPORT_RAW_INITRD 26 27 #define CONFIG_SKIP_LOWLEVEL_INIT 28 #define CONFIG_BOARD_EARLY_INIT_F 1 29 30 /* Flat Device Tree Definitions */ 31 #define CONFIG_OF_LIBFDT 32 #define CONFIG_OF_BOARD_SETUP 33 34 /* new uImage format support */ 35 #define CONFIG_FIT 36 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 37 38 #ifndef CONFIG_SYS_FSL_DDR4 39 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 40 #endif 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 47 /* Generic Timer Definitions */ 48 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 49 50 /* Size of malloc() pool */ 51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 52 53 /* Serial Port */ 54 #define CONFIG_CONS_INDEX 1 55 #define CONFIG_SYS_NS16550 56 #define CONFIG_SYS_NS16550_SERIAL 57 #define CONFIG_SYS_NS16550_REG_SIZE 1 58 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 59 60 #define CONFIG_BAUDRATE 115200 61 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 62 63 /* IFC */ 64 #define CONFIG_FSL_IFC 65 /* 66 * CONFIG_SYS_FLASH_BASE has the final address (core view) 67 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 68 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 69 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 70 */ 71 #define CONFIG_SYS_FLASH_BASE 0x60000000 72 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 73 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 74 75 #ifndef CONFIG_SYS_NO_FLASH 76 #define CONFIG_FLASH_CFI_DRIVER 77 #define CONFIG_SYS_FLASH_CFI 78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 79 #define CONFIG_SYS_FLASH_QUIET_TEST 80 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 81 #endif 82 83 /* I2C */ 84 #define CONFIG_CMD_I2C 85 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_MXC 87 #define CONFIG_SYS_I2C_MXC_I2C1 88 #define CONFIG_SYS_I2C_MXC_I2C2 89 #define CONFIG_SYS_I2C_MXC_I2C3 90 #define CONFIG_SYS_I2C_MXC_I2C4 91 92 /* PCIe */ 93 #define CONFIG_PCI /* Enable PCI/PCIE */ 94 #define CONFIG_PCIE1 /* PCIE controller 1 */ 95 #define CONFIG_PCIE2 /* PCIE controller 2 */ 96 #define CONFIG_PCIE3 /* PCIE controller 3 */ 97 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 98 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 99 100 #define CONFIG_SYS_PCI_64BIT 101 102 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 103 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 104 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 105 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 106 107 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 108 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 109 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 110 111 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 112 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 113 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 114 115 #ifdef CONFIG_PCI 116 #define CONFIG_NET_MULTI 117 #define CONFIG_PCI_PNP 118 #define CONFIG_E1000 119 #define CONFIG_PCI_SCAN_SHOW 120 #define CONFIG_CMD_PCI 121 #endif 122 123 /* Command line configuration */ 124 #define CONFIG_CMD_CACHE 125 #define CONFIG_CMD_DHCP 126 #define CONFIG_CMD_ENV 127 #define CONFIG_CMD_PING 128 129 /* Miscellaneous configurable options */ 130 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 131 #define CONFIG_ARCH_EARLY_INIT_R 132 #define CONFIG_BOARD_LATE_INIT 133 134 #define CONFIG_HWCONFIG 135 #define HWCONFIG_BUFFER_SIZE 128 136 137 /* Initial environment variables */ 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 140 "loadaddr=0x80100000\0" \ 141 "kernel_addr=0x100000\0" \ 142 "ramdisk_addr=0x800000\0" \ 143 "ramdisk_size=0x2000000\0" \ 144 "fdt_high=0xffffffffffffffff\0" \ 145 "initrd_high=0xffffffffffffffff\0" \ 146 "kernel_start=0x61200000\0" \ 147 "kernel_load=0x807f0000\0" \ 148 "kernel_size=0x1000000\0" \ 149 "console=ttyAMA0,38400n8\0" 150 151 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 152 "earlycon=uart8250,0x21c0500,115200" 153 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 154 "$kernel_size && bootm $kernel_load" 155 #define CONFIG_BOOTDELAY 10 156 157 /* Monitor Command Prompt */ 158 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 159 #define CONFIG_SYS_PROMPT "=> " 160 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 161 sizeof(CONFIG_SYS_PROMPT) + 16) 162 #define CONFIG_SYS_HUSH_PARSER 163 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 164 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 165 #define CONFIG_SYS_LONGHELP 166 #define CONFIG_CMDLINE_EDITING 1 167 #define CONFIG_AUTO_COMPLETE 168 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 169 170 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 171 172 #endif /* __LS1043A_COMMON_H */ 173