1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH2 13 #define CONFIG_LS1043A 14 #define CONFIG_MP 15 #define CONFIG_SYS_FSL_CLK 16 #define CONFIG_GICV2 17 18 #include <asm/arch/config.h> 19 #ifdef CONFIG_SYS_FSL_SRDS_1 20 #define CONFIG_SYS_HAS_SERDES 21 #endif 22 23 /* Link Definitions */ 24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 25 26 #define CONFIG_SUPPORT_RAW_INITRD 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_BOARD_EARLY_INIT_F 1 30 31 #ifndef CONFIG_SYS_FSL_DDR4 32 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 33 #endif 34 35 #define CONFIG_VERY_BIG_RAM 36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 40 41 #define CPU_RELEASE_ADDR secondary_boot_func 42 43 /* Generic Timer Definitions */ 44 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 46 /* Size of malloc() pool */ 47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 48 49 /* Serial Port */ 50 #define CONFIG_CONS_INDEX 1 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE 1 53 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 54 55 #define CONFIG_BAUDRATE 115200 56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 57 58 /* SD boot SPL */ 59 #ifdef CONFIG_SD_BOOT 60 #define CONFIG_SPL_FRAMEWORK 61 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 63 #define CONFIG_SPL_LIBCOMMON_SUPPORT 64 #define CONFIG_SPL_LIBGENERIC_SUPPORT 65 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 66 #define CONFIG_SPL_WATCHDOG_SUPPORT 67 #define CONFIG_SPL_I2C_SUPPORT 68 #define CONFIG_SPL_SERIAL_SUPPORT 69 #define CONFIG_SPL_MMC_SUPPORT 70 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 71 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 72 73 #define CONFIG_SPL_TEXT_BASE 0x10000000 74 #define CONFIG_SPL_MAX_SIZE 0x1d000 75 #define CONFIG_SPL_STACK 0x1001e000 76 #define CONFIG_SPL_PAD_TO 0x1d000 77 78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 79 CONFIG_SYS_MONITOR_LEN) 80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 83 #define CONFIG_SYS_MONITOR_LEN 0xa0000 84 #endif 85 86 /* NAND SPL */ 87 #ifdef CONFIG_NAND_BOOT 88 #define CONFIG_SPL_PBL_PAD 89 #define CONFIG_SPL_FRAMEWORK 90 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 91 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 92 #define CONFIG_SPL_LIBCOMMON_SUPPORT 93 #define CONFIG_SPL_LIBGENERIC_SUPPORT 94 #define CONFIG_SPL_WATCHDOG_SUPPORT 95 #define CONFIG_SPL_I2C_SUPPORT 96 #define CONFIG_SPL_SERIAL_SUPPORT 97 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 98 #define CONFIG_SPL_NAND_SUPPORT 99 #define CONFIG_SPL_TEXT_BASE 0x10000000 100 #define CONFIG_SPL_MAX_SIZE 0x1a000 101 #define CONFIG_SPL_STACK 0x1001d000 102 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 104 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 105 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 106 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 107 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 108 #define CONFIG_SYS_MONITOR_LEN 0xa0000 109 #endif 110 111 /* IFC */ 112 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 113 #define CONFIG_FSL_IFC 114 /* 115 * CONFIG_SYS_FLASH_BASE has the final address (core view) 116 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 117 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 118 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 119 */ 120 #define CONFIG_SYS_FLASH_BASE 0x60000000 121 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 122 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 123 124 #ifndef CONFIG_SYS_NO_FLASH 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 128 #define CONFIG_SYS_FLASH_QUIET_TEST 129 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 130 #endif 131 #endif 132 133 /* I2C */ 134 #define CONFIG_SYS_I2C 135 #define CONFIG_SYS_I2C_MXC 136 #define CONFIG_SYS_I2C_MXC_I2C1 137 #define CONFIG_SYS_I2C_MXC_I2C2 138 #define CONFIG_SYS_I2C_MXC_I2C3 139 #define CONFIG_SYS_I2C_MXC_I2C4 140 141 /* PCIe */ 142 #define CONFIG_PCI /* Enable PCI/PCIE */ 143 #define CONFIG_PCIE1 /* PCIE controller 1 */ 144 #define CONFIG_PCIE2 /* PCIE controller 2 */ 145 #define CONFIG_PCIE3 /* PCIE controller 3 */ 146 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 147 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 148 149 #define CONFIG_SYS_PCI_64BIT 150 151 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 152 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 153 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 154 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 155 156 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 157 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 158 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 159 160 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 161 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 162 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 163 164 #ifdef CONFIG_PCI 165 #define CONFIG_NET_MULTI 166 #define CONFIG_PCI_PNP 167 #define CONFIG_E1000 168 #define CONFIG_PCI_SCAN_SHOW 169 #define CONFIG_CMD_PCI 170 #endif 171 172 /* Command line configuration */ 173 #define CONFIG_CMD_ENV 174 #define CONFIG_MENU 175 #define CONFIG_CMD_PXE 176 177 /* MMC */ 178 #define CONFIG_MMC 179 #ifdef CONFIG_MMC 180 #define CONFIG_FSL_ESDHC 181 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 182 #define CONFIG_GENERIC_MMC 183 #define CONFIG_DOS_PARTITION 184 #endif 185 186 /* DSPI */ 187 #define CONFIG_FSL_DSPI 188 #ifdef CONFIG_FSL_DSPI 189 #define CONFIG_DM_SPI_FLASH 190 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 191 #define CONFIG_SPI_FLASH_SST /* cs1 */ 192 #define CONFIG_SPI_FLASH_EON /* cs2 */ 193 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 194 #define CONFIG_SF_DEFAULT_BUS 1 195 #define CONFIG_SF_DEFAULT_CS 0 196 #endif 197 #endif 198 199 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 200 201 /* FMan ucode */ 202 #define CONFIG_SYS_DPAA_FMAN 203 #ifdef CONFIG_SYS_DPAA_FMAN 204 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 205 206 #ifdef CONFIG_NAND_BOOT 207 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 208 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 209 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 210 #elif defined(CONFIG_SD_BOOT) 211 /* 212 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 213 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 214 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 215 */ 216 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 217 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 218 #elif defined(CONFIG_QSPI_BOOT) 219 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 220 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 221 #define CONFIG_ENV_SPI_BUS 0 222 #define CONFIG_ENV_SPI_CS 0 223 #define CONFIG_ENV_SPI_MAX_HZ 1000000 224 #define CONFIG_ENV_SPI_MODE 0x03 225 #else 226 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 227 /* FMan fireware Pre-load address */ 228 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 229 #endif 230 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 231 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 232 #endif 233 234 /* Miscellaneous configurable options */ 235 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 236 #define CONFIG_ARCH_EARLY_INIT_R 237 #define CONFIG_BOARD_LATE_INIT 238 239 #define CONFIG_HWCONFIG 240 #define HWCONFIG_BUFFER_SIZE 128 241 242 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 243 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 244 "5m(kernel),1m(dtb),9m(file_system)" 245 #else 246 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 247 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 248 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 249 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 250 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 251 "40m(nor_bank4_fit);7e800000.flash:" \ 252 "1m(nand_uboot),1m(nand_uboot_env)," \ 253 "20m(nand_fit);spi0.0:1m(uboot)," \ 254 "5m(kernel),1m(dtb),9m(file_system)" 255 #endif 256 257 /* Initial environment variables */ 258 #define CONFIG_EXTRA_ENV_SETTINGS \ 259 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 260 "loadaddr=0x80100000\0" \ 261 "fdt_high=0xffffffffffffffff\0" \ 262 "initrd_high=0xffffffffffffffff\0" \ 263 "kernel_start=0x61100000\0" \ 264 "kernel_load=0xa0000000\0" \ 265 "kernel_size=0x2800000\0" \ 266 "console=ttyS0,115200\0" \ 267 "mtdparts=" MTDPARTS_DEFAULT "\0" 268 269 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 270 "earlycon=uart8250,mmio,0x21c0500 " \ 271 MTDPARTS_DEFAULT 272 273 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 274 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 275 "e0000 f00000 && bootm $kernel_load" 276 #else 277 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 278 "$kernel_size && bootm $kernel_load" 279 #endif 280 281 /* Monitor Command Prompt */ 282 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 283 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 284 sizeof(CONFIG_SYS_PROMPT) + 16) 285 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 286 #define CONFIG_SYS_LONGHELP 287 #define CONFIG_CMDLINE_EDITING 1 288 #define CONFIG_AUTO_COMPLETE 289 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 290 291 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 292 293 /* Hash command with SHA acceleration supported in hardware */ 294 #ifdef CONFIG_FSL_CAAM 295 #define CONFIG_CMD_HASH 296 #define CONFIG_SHA_HW_ACCEL 297 #endif 298 299 #endif /* __LS1043A_COMMON_H */ 300