1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_BOARD_EARLY_INIT_F 22 #define CONFIG_DEEP_SLEEP 23 #ifdef CONFIG_DEEP_SLEEP 24 #define CONFIG_SILENT_CONSOLE 25 #endif 26 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 31 32 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 33 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 34 35 /* 36 * USB 37 */ 38 39 /* 40 * EHCI Support - disbaled by default as 41 * there is no signal coming out of soc on 42 * this board for this controller. However, 43 * the silicon still has this controller, 44 * and anyone can use this controller by 45 * taking signals out on their board. 46 */ 47 48 /*#define CONFIG_HAS_FSL_DR_USB*/ 49 50 #ifdef CONFIG_HAS_FSL_DR_USB 51 #define CONFIG_USB_EHCI 52 #define CONFIG_USB_EHCI_FSL 53 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 54 #endif 55 56 /* XHCI Support - enabled by default */ 57 #define CONFIG_HAS_FSL_XHCI_USB 58 59 #ifdef CONFIG_HAS_FSL_XHCI_USB 60 #define CONFIG_USB_XHCI_FSL 61 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 62 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 63 #endif 64 65 /* 66 * Generic Timer Definitions 67 */ 68 #define GENERIC_TIMER_CLK 12500000 69 70 #define CONFIG_SYS_CLK_FREQ 100000000 71 #define CONFIG_DDR_CLK_FREQ 100000000 72 73 #define DDR_SDRAM_CFG 0x470c0008 74 #define DDR_CS0_BNDS 0x008000bf 75 #define DDR_CS0_CONFIG 0x80014302 76 #define DDR_TIMING_CFG_0 0x50550004 77 #define DDR_TIMING_CFG_1 0xbcb38c56 78 #define DDR_TIMING_CFG_2 0x0040d120 79 #define DDR_TIMING_CFG_3 0x010e1000 80 #define DDR_TIMING_CFG_4 0x00000001 81 #define DDR_TIMING_CFG_5 0x03401400 82 #define DDR_SDRAM_CFG_2 0x00401010 83 #define DDR_SDRAM_MODE 0x00061c60 84 #define DDR_SDRAM_MODE_2 0x00180000 85 #define DDR_SDRAM_INTERVAL 0x18600618 86 #define DDR_DDR_WRLVL_CNTL 0x8655f605 87 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 88 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 89 #define DDR_DDR_CDR1 0x80040000 90 #define DDR_DDR_CDR2 0x00000001 91 #define DDR_SDRAM_CLK_CNTL 0x02000000 92 #define DDR_DDR_ZQ_CNTL 0x89080600 93 #define DDR_CS0_CONFIG_2 0 94 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 95 #define SDRAM_CFG2_D_INIT 0x00000010 96 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 97 #define SDRAM_CFG2_FRC_SR 0x80000000 98 #define SDRAM_CFG_BI 0x00000001 99 100 #ifdef CONFIG_RAMBOOT_PBL 101 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 102 #endif 103 104 #ifdef CONFIG_SD_BOOT 105 #ifdef CONFIG_SD_BOOT_QSPI 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 108 #else 109 #define CONFIG_SYS_FSL_PBL_RCW \ 110 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 111 #endif 112 #define CONFIG_SPL_FRAMEWORK 113 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 114 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 115 116 #ifdef CONFIG_SECURE_BOOT 117 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 118 /* 119 * HDR would be appended at end of image and copied to DDR along 120 * with U-Boot image. 121 */ 122 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 123 (CONFIG_U_BOOT_HDR_SIZE / 512) 124 #else 125 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 126 #endif /* ifdef CONFIG_SECURE_BOOT */ 127 128 #define CONFIG_SPL_TEXT_BASE 0x10000000 129 #define CONFIG_SPL_MAX_SIZE 0x1a000 130 #define CONFIG_SPL_STACK 0x1001d000 131 #define CONFIG_SPL_PAD_TO 0x1c000 132 #define CONFIG_SYS_TEXT_BASE 0x82000000 133 134 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 135 CONFIG_SYS_MONITOR_LEN) 136 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 137 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 138 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 139 140 #ifdef CONFIG_U_BOOT_HDR_SIZE 141 /* 142 * HDR would be appended at end of image and copied to DDR along 143 * with U-Boot image. Here u-boot max. size is 512K. So if binary 144 * size increases then increase this size in case of secure boot as 145 * it uses raw u-boot image instead of fit image. 146 */ 147 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 148 #else 149 #define CONFIG_SYS_MONITOR_LEN 0x80000 150 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 151 #endif 152 153 #ifdef CONFIG_QSPI_BOOT 154 #define CONFIG_SYS_TEXT_BASE 0x40010000 155 #endif 156 157 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 158 #define CONFIG_SYS_NO_FLASH 159 #endif 160 161 #ifndef CONFIG_SYS_TEXT_BASE 162 #define CONFIG_SYS_TEXT_BASE 0x60100000 163 #endif 164 165 #define CONFIG_NR_DRAM_BANKS 1 166 #define PHYS_SDRAM 0x80000000 167 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 168 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 #define CONFIG_SYS_HAS_SERDES 173 174 #define CONFIG_FSL_CAAM /* Enable CAAM */ 175 176 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 177 !defined(CONFIG_QSPI_BOOT) 178 #define CONFIG_U_QE 179 #endif 180 181 /* 182 * IFC Definitions 183 */ 184 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 185 #define CONFIG_FSL_IFC 186 #define CONFIG_SYS_FLASH_BASE 0x60000000 187 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 188 189 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 190 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 191 CSPR_PORT_SIZE_16 | \ 192 CSPR_MSEL_NOR | \ 193 CSPR_V) 194 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 195 196 /* NOR Flash Timing Params */ 197 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 198 CSOR_NOR_TRHZ_80) 199 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 200 FTIM0_NOR_TEADC(0x5) | \ 201 FTIM0_NOR_TAVDS(0x0) | \ 202 FTIM0_NOR_TEAHC(0x5)) 203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 204 FTIM1_NOR_TRAD_NOR(0x1A) | \ 205 FTIM1_NOR_TSEQRAD_NOR(0x13)) 206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 207 FTIM2_NOR_TCH(0x4) | \ 208 FTIM2_NOR_TWP(0x1c) | \ 209 FTIM2_NOR_TWPH(0x0e)) 210 #define CONFIG_SYS_NOR_FTIM3 0 211 212 #define CONFIG_FLASH_CFI_DRIVER 213 #define CONFIG_SYS_FLASH_CFI 214 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 222 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 225 226 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 227 #define CONFIG_SYS_WRITE_SWAPPED_DATA 228 #endif 229 230 /* CPLD */ 231 232 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 233 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 234 235 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 236 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 237 CSPR_PORT_SIZE_8 | \ 238 CSPR_MSEL_GPCM | \ 239 CSPR_V) 240 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 241 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 242 CSOR_NOR_NOR_MODE_AVD_NOR | \ 243 CSOR_NOR_TRHZ_80) 244 245 /* CPLD Timing parameters for IFC GPCM */ 246 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 247 FTIM0_GPCM_TEADC(0xf) | \ 248 FTIM0_GPCM_TEAHC(0xf)) 249 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 250 FTIM1_GPCM_TRAD(0x3f)) 251 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 252 FTIM2_GPCM_TCH(0xf) | \ 253 FTIM2_GPCM_TWP(0xff)) 254 #define CONFIG_SYS_FPGA_FTIM3 0x0 255 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 256 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 257 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 258 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 263 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 264 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 265 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 266 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 267 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 268 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 269 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 270 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 271 272 /* 273 * Serial Port 274 */ 275 #ifdef CONFIG_LPUART 276 #define CONFIG_LPUART_32B_REG 277 #else 278 #define CONFIG_CONS_INDEX 1 279 #define CONFIG_SYS_NS16550_SERIAL 280 #ifndef CONFIG_DM_SERIAL 281 #define CONFIG_SYS_NS16550_REG_SIZE 1 282 #endif 283 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 284 #endif 285 286 #define CONFIG_BAUDRATE 115200 287 288 /* 289 * I2C 290 */ 291 #define CONFIG_SYS_I2C 292 #define CONFIG_SYS_I2C_MXC 293 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 294 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 295 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 296 297 /* EEPROM */ 298 #define CONFIG_ID_EEPROM 299 #define CONFIG_SYS_I2C_EEPROM_NXID 300 #define CONFIG_SYS_EEPROM_BUS_NUM 1 301 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 302 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 303 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 305 306 /* 307 * MMC 308 */ 309 #define CONFIG_MMC 310 #define CONFIG_FSL_ESDHC 311 #define CONFIG_GENERIC_MMC 312 313 #define CONFIG_DOS_PARTITION 314 315 /* SPI */ 316 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 317 /* QSPI */ 318 #define QSPI0_AMBA_BASE 0x40000000 319 #define FSL_QSPI_FLASH_SIZE (1 << 24) 320 #define FSL_QSPI_FLASH_NUM 2 321 322 /* DSPI */ 323 #endif 324 325 /* DM SPI */ 326 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 327 #define CONFIG_DM_SPI_FLASH 328 #endif 329 330 /* 331 * Video 332 */ 333 #define CONFIG_FSL_DCU_FB 334 335 #ifdef CONFIG_FSL_DCU_FB 336 #define CONFIG_VIDEO 337 #define CONFIG_CMD_BMP 338 #define CONFIG_CFB_CONSOLE 339 #define CONFIG_VGA_AS_SINGLE_DEVICE 340 #define CONFIG_VIDEO_LOGO 341 #define CONFIG_VIDEO_BMP_LOGO 342 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 343 344 #define CONFIG_FSL_DCU_SII9022A 345 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 346 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 347 #endif 348 349 /* 350 * eTSEC 351 */ 352 #define CONFIG_TSEC_ENET 353 354 #ifdef CONFIG_TSEC_ENET 355 #define CONFIG_MII 356 #define CONFIG_MII_DEFAULT_TSEC 1 357 #define CONFIG_TSEC1 1 358 #define CONFIG_TSEC1_NAME "eTSEC1" 359 #define CONFIG_TSEC2 1 360 #define CONFIG_TSEC2_NAME "eTSEC2" 361 #define CONFIG_TSEC3 1 362 #define CONFIG_TSEC3_NAME "eTSEC3" 363 364 #define TSEC1_PHY_ADDR 2 365 #define TSEC2_PHY_ADDR 0 366 #define TSEC3_PHY_ADDR 1 367 368 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 369 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 370 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 371 372 #define TSEC1_PHYIDX 0 373 #define TSEC2_PHYIDX 0 374 #define TSEC3_PHYIDX 0 375 376 #define CONFIG_ETHPRIME "eTSEC1" 377 378 #define CONFIG_PHY_GIGE 379 #define CONFIG_PHYLIB 380 #define CONFIG_PHY_ATHEROS 381 382 #define CONFIG_HAS_ETH0 383 #define CONFIG_HAS_ETH1 384 #define CONFIG_HAS_ETH2 385 #endif 386 387 /* PCIe */ 388 #define CONFIG_PCI /* Enable PCI/PCIE */ 389 #define CONFIG_PCIE1 /* PCIE controller 1 */ 390 #define CONFIG_PCIE2 /* PCIE controller 2 */ 391 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 392 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 393 394 #define CONFIG_SYS_PCI_64BIT 395 396 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 397 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 398 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 399 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 400 401 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 402 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 403 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 404 405 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 406 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 407 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 408 409 #ifdef CONFIG_PCI 410 #define CONFIG_PCI_PNP 411 #define CONFIG_PCI_SCAN_SHOW 412 #define CONFIG_CMD_PCI 413 #endif 414 415 #define CONFIG_CMDLINE_TAG 416 #define CONFIG_CMDLINE_EDITING 417 418 #define CONFIG_PEN_ADDR_BIG_ENDIAN 419 #define CONFIG_LAYERSCAPE_NS_ACCESS 420 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 421 #define CONFIG_TIMER_CLK_FREQ 12500000 422 423 #define CONFIG_HWCONFIG 424 #define HWCONFIG_BUFFER_SIZE 256 425 426 #define CONFIG_FSL_DEVICE_DISABLE 427 428 429 #ifdef CONFIG_LPUART 430 #define CONFIG_EXTRA_ENV_SETTINGS \ 431 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 432 "initrd_high=0xffffffff\0" \ 433 "fdt_high=0xffffffff\0" 434 #else 435 #define CONFIG_EXTRA_ENV_SETTINGS \ 436 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 437 "initrd_high=0xffffffff\0" \ 438 "fdt_high=0xffffffff\0" 439 #endif 440 441 /* 442 * Miscellaneous configurable options 443 */ 444 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 445 #define CONFIG_AUTO_COMPLETE 446 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 447 #define CONFIG_SYS_PBSIZE \ 448 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 449 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 450 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 451 452 #define CONFIG_SYS_MEMTEST_START 0x80000000 453 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 454 455 #define CONFIG_SYS_LOAD_ADDR 0x82000000 456 457 #define CONFIG_LS102XA_STREAM_ID 458 459 /* 460 * Stack sizes 461 * The stack sizes are set up in start.S using the settings below 462 */ 463 #define CONFIG_STACKSIZE (30 * 1024) 464 465 #define CONFIG_SYS_INIT_SP_OFFSET \ 466 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 467 #define CONFIG_SYS_INIT_SP_ADDR \ 468 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 469 470 #ifdef CONFIG_SPL_BUILD 471 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 472 #else 473 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 474 #endif 475 476 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 477 478 /* 479 * Environment 480 */ 481 #define CONFIG_ENV_OVERWRITE 482 483 #if defined(CONFIG_SD_BOOT) 484 #define CONFIG_ENV_OFFSET 0x100000 485 #define CONFIG_ENV_IS_IN_MMC 486 #define CONFIG_SYS_MMC_ENV_DEV 0 487 #define CONFIG_ENV_SIZE 0x20000 488 #elif defined(CONFIG_QSPI_BOOT) 489 #define CONFIG_ENV_IS_IN_SPI_FLASH 490 #define CONFIG_ENV_SIZE 0x2000 491 #define CONFIG_ENV_OFFSET 0x100000 492 #define CONFIG_ENV_SECT_SIZE 0x10000 493 #else 494 #define CONFIG_ENV_IS_IN_FLASH 495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 496 #define CONFIG_ENV_SIZE 0x20000 497 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 498 #endif 499 500 #define CONFIG_MISC_INIT_R 501 502 /* Hash command with SHA acceleration supported in hardware */ 503 #ifdef CONFIG_FSL_CAAM 504 #define CONFIG_CMD_HASH 505 #define CONFIG_SHA_HW_ACCEL 506 #endif 507 508 #include <asm/fsl_secure_boot.h> 509 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 510 511 #endif 512