1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #define CONFIG_SYS_CLK_FREQ 100000000 36 #define CONFIG_DDR_CLK_FREQ 100000000 37 38 #ifndef CONFIG_SYS_TEXT_BASE 39 #define CONFIG_SYS_TEXT_BASE 0x67f80000 40 #endif 41 42 #define CONFIG_NR_DRAM_BANKS 1 43 #define PHYS_SDRAM 0x80000000 44 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 45 46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 49 #define CONFIG_SYS_HAS_SERDES 50 51 /* 52 * IFC Definitions 53 */ 54 #define CONFIG_FSL_IFC 55 #define CONFIG_SYS_FLASH_BASE 0x60000000 56 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 57 58 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 59 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 60 CSPR_PORT_SIZE_16 | \ 61 CSPR_MSEL_NOR | \ 62 CSPR_V) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 64 65 /* NOR Flash Timing Params */ 66 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 67 CSOR_NOR_TRHZ_80) 68 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 69 FTIM0_NOR_TEADC(0x5) | \ 70 FTIM0_NOR_TAVDS(0x0) | \ 71 FTIM0_NOR_TEAHC(0x5)) 72 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 73 FTIM1_NOR_TRAD_NOR(0x1A) | \ 74 FTIM1_NOR_TSEQRAD_NOR(0x13)) 75 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 76 FTIM2_NOR_TCH(0x4) | \ 77 FTIM2_NOR_TWP(0x1c) | \ 78 FTIM2_NOR_TWPH(0x0e)) 79 #define CONFIG_SYS_NOR_FTIM3 0 80 81 #define CONFIG_FLASH_CFI_DRIVER 82 #define CONFIG_SYS_FLASH_CFI 83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 84 #define CONFIG_SYS_FLASH_QUIET_TEST 85 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 86 87 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 91 92 #define CONFIG_SYS_FLASH_EMPTY_INFO 93 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 94 95 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 96 97 /* CPLD */ 98 99 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 100 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 101 102 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 103 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 104 CSPR_PORT_SIZE_8 | \ 105 CSPR_MSEL_GPCM | \ 106 CSPR_V) 107 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 108 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 109 CSOR_NOR_NOR_MODE_AVD_NOR | \ 110 CSOR_NOR_TRHZ_80) 111 112 /* CPLD Timing parameters for IFC GPCM */ 113 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 114 FTIM0_GPCM_TEADC(0xf) | \ 115 FTIM0_GPCM_TEAHC(0xf)) 116 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 117 FTIM1_GPCM_TRAD(0x3f)) 118 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 119 FTIM2_GPCM_TCH(0xf) | \ 120 FTIM2_GPCM_TWP(0xff)) 121 #define CONFIG_SYS_FPGA_FTIM3 0x0 122 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 123 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 124 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 125 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 126 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 127 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 128 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 129 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 130 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 131 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 132 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 133 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 134 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 135 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 136 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 137 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 138 139 /* 140 * Serial Port 141 */ 142 #define CONFIG_CONS_INDEX 1 143 #define CONFIG_SYS_NS16550 144 #define CONFIG_SYS_NS16550_SERIAL 145 #define CONFIG_SYS_NS16550_REG_SIZE 1 146 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 147 148 #define CONFIG_BAUDRATE 115200 149 150 /* 151 * I2C 152 */ 153 #define CONFIG_CMD_I2C 154 #define CONFIG_SYS_I2C 155 #define CONFIG_SYS_I2C_MXC 156 157 /* 158 * MMC 159 */ 160 #define CONFIG_MMC 161 #define CONFIG_CMD_MMC 162 #define CONFIG_FSL_ESDHC 163 #define CONFIG_GENERIC_MMC 164 165 /* 166 * eTSEC 167 */ 168 #define CONFIG_TSEC_ENET 169 170 #ifdef CONFIG_TSEC_ENET 171 #define CONFIG_MII 172 #define CONFIG_MII_DEFAULT_TSEC 1 173 #define CONFIG_TSEC1 1 174 #define CONFIG_TSEC1_NAME "eTSEC1" 175 #define CONFIG_TSEC2 1 176 #define CONFIG_TSEC2_NAME "eTSEC2" 177 #define CONFIG_TSEC3 1 178 #define CONFIG_TSEC3_NAME "eTSEC3" 179 180 #define TSEC1_PHY_ADDR 2 181 #define TSEC2_PHY_ADDR 0 182 #define TSEC3_PHY_ADDR 1 183 184 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 185 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 186 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 187 188 #define TSEC1_PHYIDX 0 189 #define TSEC2_PHYIDX 0 190 #define TSEC3_PHYIDX 0 191 192 #define CONFIG_ETHPRIME "eTSEC1" 193 194 #define CONFIG_PHY_GIGE 195 #define CONFIG_PHYLIB 196 #define CONFIG_PHY_ATHEROS 197 198 #define CONFIG_HAS_ETH0 199 #define CONFIG_HAS_ETH1 200 #define CONFIG_HAS_ETH2 201 #endif 202 203 #define CONFIG_CMD_PING 204 #define CONFIG_CMD_DHCP 205 #define CONFIG_CMD_MII 206 #define CONFIG_CMD_NET 207 208 #define CONFIG_CMDLINE_TAG 209 #define CONFIG_CMDLINE_EDITING 210 #define CONFIG_CMD_IMLS 211 212 #define CONFIG_HWCONFIG 213 #define HWCONFIG_BUFFER_SIZE 128 214 215 #define CONFIG_BOOTDELAY 3 216 217 #define CONFIG_EXTRA_ENV_SETTINGS \ 218 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 219 "initrd_high=0xcfffffff\0" \ 220 "fdt_high=0xcfffffff\0" 221 222 /* 223 * Miscellaneous configurable options 224 */ 225 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 226 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 227 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 228 #define CONFIG_SYS_PROMPT "=> " 229 #define CONFIG_AUTO_COMPLETE 230 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 231 #define CONFIG_SYS_PBSIZE \ 232 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 233 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 234 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 235 236 #define CONFIG_CMD_ENV_EXISTS 237 #define CONFIG_CMD_GREPENV 238 #define CONFIG_CMD_MEMINFO 239 #define CONFIG_CMD_MEMTEST 240 #define CONFIG_SYS_MEMTEST_START 0x80000000 241 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 242 243 #define CONFIG_SYS_LOAD_ADDR 0x82000000 244 #define CONFIG_SYS_HZ 1000 245 246 /* 247 * Stack sizes 248 * The stack sizes are set up in start.S using the settings below 249 */ 250 #define CONFIG_STACKSIZE (30 * 1024) 251 252 #define CONFIG_SYS_INIT_SP_OFFSET \ 253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 254 #define CONFIG_SYS_INIT_SP_ADDR \ 255 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 256 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 258 259 /* 260 * Environment 261 */ 262 #define CONFIG_ENV_OVERWRITE 263 264 #define CONFIG_ENV_IS_IN_FLASH 265 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 266 #define CONFIG_ENV_SIZE 0x20000 267 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 268 269 #define CONFIG_OF_LIBFDT 270 #define CONFIG_OF_BOARD_SETUP 271 #define CONFIG_CMD_BOOTZ 272 273 #endif 274