1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 #define CONFIG_DEEP_SLEEP 24 #ifdef CONFIG_DEEP_SLEEP 25 #define CONFIG_SILENT_CONSOLE 26 #endif 27 28 /* 29 * Size of malloc() pool 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 32 33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 35 36 /* 37 * USB 38 */ 39 40 /* 41 * EHCI Support - disbaled by default as 42 * there is no signal coming out of soc on 43 * this board for this controller. However, 44 * the silicon still has this controller, 45 * and anyone can use this controller by 46 * taking signals out on their board. 47 */ 48 49 /*#define CONFIG_HAS_FSL_DR_USB*/ 50 51 #ifdef CONFIG_HAS_FSL_DR_USB 52 #define CONFIG_USB_EHCI 53 #define CONFIG_USB_EHCI_FSL 54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 55 #endif 56 57 /* XHCI Support - enabled by default */ 58 #define CONFIG_HAS_FSL_XHCI_USB 59 60 #ifdef CONFIG_HAS_FSL_XHCI_USB 61 #define CONFIG_USB_XHCI_FSL 62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 64 #endif 65 66 /* 67 * Generic Timer Definitions 68 */ 69 #define GENERIC_TIMER_CLK 12500000 70 71 #define CONFIG_SYS_CLK_FREQ 100000000 72 #define CONFIG_DDR_CLK_FREQ 100000000 73 74 #define DDR_SDRAM_CFG 0x470c0008 75 #define DDR_CS0_BNDS 0x008000bf 76 #define DDR_CS0_CONFIG 0x80014302 77 #define DDR_TIMING_CFG_0 0x50550004 78 #define DDR_TIMING_CFG_1 0xbcb38c56 79 #define DDR_TIMING_CFG_2 0x0040d120 80 #define DDR_TIMING_CFG_3 0x010e1000 81 #define DDR_TIMING_CFG_4 0x00000001 82 #define DDR_TIMING_CFG_5 0x03401400 83 #define DDR_SDRAM_CFG_2 0x00401010 84 #define DDR_SDRAM_MODE 0x00061c60 85 #define DDR_SDRAM_MODE_2 0x00180000 86 #define DDR_SDRAM_INTERVAL 0x18600618 87 #define DDR_DDR_WRLVL_CNTL 0x8655f605 88 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 89 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 90 #define DDR_DDR_CDR1 0x80040000 91 #define DDR_DDR_CDR2 0x00000001 92 #define DDR_SDRAM_CLK_CNTL 0x02000000 93 #define DDR_DDR_ZQ_CNTL 0x89080600 94 #define DDR_CS0_CONFIG_2 0 95 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 96 #define SDRAM_CFG2_D_INIT 0x00000010 97 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 98 #define SDRAM_CFG2_FRC_SR 0x80000000 99 #define SDRAM_CFG_BI 0x00000001 100 101 #ifdef CONFIG_RAMBOOT_PBL 102 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 103 #endif 104 105 #ifdef CONFIG_SD_BOOT 106 #ifdef CONFIG_SD_BOOT_QSPI 107 #define CONFIG_SYS_FSL_PBL_RCW \ 108 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 109 #else 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 112 #endif 113 #define CONFIG_SPL_FRAMEWORK 114 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 115 #define CONFIG_SPL_LIBCOMMON_SUPPORT 116 #define CONFIG_SPL_LIBGENERIC_SUPPORT 117 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 118 #define CONFIG_SPL_I2C_SUPPORT 119 #define CONFIG_SPL_WATCHDOG_SUPPORT 120 #define CONFIG_SPL_SERIAL_SUPPORT 121 #define CONFIG_SPL_MMC_SUPPORT 122 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 123 124 #ifdef CONFIG_SECURE_BOOT 125 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 126 /* 127 * HDR would be appended at end of image and copied to DDR along 128 * with U-Boot image. 129 */ 130 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 131 (CONFIG_U_BOOT_HDR_SIZE / 512) 132 #else 133 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 134 #endif /* ifdef CONFIG_SECURE_BOOT */ 135 136 #define CONFIG_SPL_TEXT_BASE 0x10000000 137 #define CONFIG_SPL_MAX_SIZE 0x1a000 138 #define CONFIG_SPL_STACK 0x1001d000 139 #define CONFIG_SPL_PAD_TO 0x1c000 140 #define CONFIG_SYS_TEXT_BASE 0x82000000 141 142 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 143 CONFIG_SYS_MONITOR_LEN) 144 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 145 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 146 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 147 148 #ifdef CONFIG_U_BOOT_HDR_SIZE 149 /* 150 * HDR would be appended at end of image and copied to DDR along 151 * with U-Boot image. Here u-boot max. size is 512K. So if binary 152 * size increases then increase this size in case of secure boot as 153 * it uses raw u-boot image instead of fit image. 154 */ 155 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 156 #else 157 #define CONFIG_SYS_MONITOR_LEN 0x80000 158 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 159 #endif 160 161 #ifdef CONFIG_QSPI_BOOT 162 #define CONFIG_SYS_TEXT_BASE 0x40010000 163 #endif 164 165 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 166 #define CONFIG_SYS_NO_FLASH 167 #endif 168 169 #ifndef CONFIG_SYS_TEXT_BASE 170 #define CONFIG_SYS_TEXT_BASE 0x60100000 171 #endif 172 173 #define CONFIG_NR_DRAM_BANKS 1 174 #define PHYS_SDRAM 0x80000000 175 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 176 177 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 178 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 179 180 #define CONFIG_SYS_HAS_SERDES 181 182 #define CONFIG_FSL_CAAM /* Enable CAAM */ 183 184 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 185 !defined(CONFIG_QSPI_BOOT) 186 #define CONFIG_U_QE 187 #endif 188 189 /* 190 * IFC Definitions 191 */ 192 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 193 #define CONFIG_FSL_IFC 194 #define CONFIG_SYS_FLASH_BASE 0x60000000 195 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 196 197 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 198 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 199 CSPR_PORT_SIZE_16 | \ 200 CSPR_MSEL_NOR | \ 201 CSPR_V) 202 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 203 204 /* NOR Flash Timing Params */ 205 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 206 CSOR_NOR_TRHZ_80) 207 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 208 FTIM0_NOR_TEADC(0x5) | \ 209 FTIM0_NOR_TAVDS(0x0) | \ 210 FTIM0_NOR_TEAHC(0x5)) 211 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 212 FTIM1_NOR_TRAD_NOR(0x1A) | \ 213 FTIM1_NOR_TSEQRAD_NOR(0x13)) 214 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 215 FTIM2_NOR_TCH(0x4) | \ 216 FTIM2_NOR_TWP(0x1c) | \ 217 FTIM2_NOR_TWPH(0x0e)) 218 #define CONFIG_SYS_NOR_FTIM3 0 219 220 #define CONFIG_FLASH_CFI_DRIVER 221 #define CONFIG_SYS_FLASH_CFI 222 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 223 #define CONFIG_SYS_FLASH_QUIET_TEST 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 225 226 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #define CONFIG_SYS_FLASH_EMPTY_INFO 232 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 233 234 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 235 #define CONFIG_SYS_WRITE_SWAPPED_DATA 236 #endif 237 238 /* CPLD */ 239 240 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 241 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 242 243 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 244 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 245 CSPR_PORT_SIZE_8 | \ 246 CSPR_MSEL_GPCM | \ 247 CSPR_V) 248 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 249 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 250 CSOR_NOR_NOR_MODE_AVD_NOR | \ 251 CSOR_NOR_TRHZ_80) 252 253 /* CPLD Timing parameters for IFC GPCM */ 254 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 255 FTIM0_GPCM_TEADC(0xf) | \ 256 FTIM0_GPCM_TEAHC(0xf)) 257 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 258 FTIM1_GPCM_TRAD(0x3f)) 259 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 260 FTIM2_GPCM_TCH(0xf) | \ 261 FTIM2_GPCM_TWP(0xff)) 262 #define CONFIG_SYS_FPGA_FTIM3 0x0 263 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 264 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 265 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 266 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 271 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 272 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 273 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 274 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 275 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 276 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 277 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 278 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 279 280 /* 281 * Serial Port 282 */ 283 #ifdef CONFIG_LPUART 284 #define CONFIG_LPUART_32B_REG 285 #else 286 #define CONFIG_CONS_INDEX 1 287 #define CONFIG_SYS_NS16550_SERIAL 288 #ifndef CONFIG_DM_SERIAL 289 #define CONFIG_SYS_NS16550_REG_SIZE 1 290 #endif 291 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 292 #endif 293 294 #define CONFIG_BAUDRATE 115200 295 296 /* 297 * I2C 298 */ 299 #define CONFIG_SYS_I2C 300 #define CONFIG_SYS_I2C_MXC 301 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 302 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 303 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 304 305 /* EEPROM */ 306 #define CONFIG_ID_EEPROM 307 #define CONFIG_SYS_I2C_EEPROM_NXID 308 #define CONFIG_SYS_EEPROM_BUS_NUM 1 309 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 310 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 313 314 /* 315 * MMC 316 */ 317 #define CONFIG_MMC 318 #define CONFIG_FSL_ESDHC 319 #define CONFIG_GENERIC_MMC 320 321 #define CONFIG_DOS_PARTITION 322 323 /* SPI */ 324 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 325 /* QSPI */ 326 #define QSPI0_AMBA_BASE 0x40000000 327 #define FSL_QSPI_FLASH_SIZE (1 << 24) 328 #define FSL_QSPI_FLASH_NUM 2 329 330 /* DSPI */ 331 #endif 332 333 /* DM SPI */ 334 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 335 #define CONFIG_DM_SPI_FLASH 336 #endif 337 338 /* 339 * Video 340 */ 341 #define CONFIG_FSL_DCU_FB 342 343 #ifdef CONFIG_FSL_DCU_FB 344 #define CONFIG_VIDEO 345 #define CONFIG_CMD_BMP 346 #define CONFIG_CFB_CONSOLE 347 #define CONFIG_VGA_AS_SINGLE_DEVICE 348 #define CONFIG_VIDEO_LOGO 349 #define CONFIG_VIDEO_BMP_LOGO 350 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 351 352 #define CONFIG_FSL_DCU_SII9022A 353 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 354 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 355 #endif 356 357 /* 358 * eTSEC 359 */ 360 #define CONFIG_TSEC_ENET 361 362 #ifdef CONFIG_TSEC_ENET 363 #define CONFIG_MII 364 #define CONFIG_MII_DEFAULT_TSEC 1 365 #define CONFIG_TSEC1 1 366 #define CONFIG_TSEC1_NAME "eTSEC1" 367 #define CONFIG_TSEC2 1 368 #define CONFIG_TSEC2_NAME "eTSEC2" 369 #define CONFIG_TSEC3 1 370 #define CONFIG_TSEC3_NAME "eTSEC3" 371 372 #define TSEC1_PHY_ADDR 2 373 #define TSEC2_PHY_ADDR 0 374 #define TSEC3_PHY_ADDR 1 375 376 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 377 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 378 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 379 380 #define TSEC1_PHYIDX 0 381 #define TSEC2_PHYIDX 0 382 #define TSEC3_PHYIDX 0 383 384 #define CONFIG_ETHPRIME "eTSEC1" 385 386 #define CONFIG_PHY_GIGE 387 #define CONFIG_PHYLIB 388 #define CONFIG_PHY_ATHEROS 389 390 #define CONFIG_HAS_ETH0 391 #define CONFIG_HAS_ETH1 392 #define CONFIG_HAS_ETH2 393 #endif 394 395 /* PCIe */ 396 #define CONFIG_PCI /* Enable PCI/PCIE */ 397 #define CONFIG_PCIE1 /* PCIE controller 1 */ 398 #define CONFIG_PCIE2 /* PCIE controller 2 */ 399 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 400 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 401 402 #define CONFIG_SYS_PCI_64BIT 403 404 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 405 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 406 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 407 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 408 409 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 410 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 411 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 412 413 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 414 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 415 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 416 417 #ifdef CONFIG_PCI 418 #define CONFIG_PCI_PNP 419 #define CONFIG_PCI_SCAN_SHOW 420 #define CONFIG_CMD_PCI 421 #endif 422 423 #define CONFIG_CMDLINE_TAG 424 #define CONFIG_CMDLINE_EDITING 425 426 #define CONFIG_ARMV7_NONSEC 427 #define CONFIG_ARMV7_VIRT 428 #define CONFIG_PEN_ADDR_BIG_ENDIAN 429 #define CONFIG_LAYERSCAPE_NS_ACCESS 430 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 431 #define CONFIG_TIMER_CLK_FREQ 12500000 432 433 #define CONFIG_HWCONFIG 434 #define HWCONFIG_BUFFER_SIZE 256 435 436 #define CONFIG_FSL_DEVICE_DISABLE 437 438 439 #ifdef CONFIG_LPUART 440 #define CONFIG_EXTRA_ENV_SETTINGS \ 441 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 442 "initrd_high=0xffffffff\0" \ 443 "fdt_high=0xffffffff\0" 444 #else 445 #define CONFIG_EXTRA_ENV_SETTINGS \ 446 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 447 "initrd_high=0xffffffff\0" \ 448 "fdt_high=0xffffffff\0" 449 #endif 450 451 /* 452 * Miscellaneous configurable options 453 */ 454 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 455 #define CONFIG_AUTO_COMPLETE 456 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 457 #define CONFIG_SYS_PBSIZE \ 458 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 459 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 460 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 461 462 #define CONFIG_SYS_MEMTEST_START 0x80000000 463 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 464 465 #define CONFIG_SYS_LOAD_ADDR 0x82000000 466 467 #define CONFIG_LS102XA_STREAM_ID 468 469 /* 470 * Stack sizes 471 * The stack sizes are set up in start.S using the settings below 472 */ 473 #define CONFIG_STACKSIZE (30 * 1024) 474 475 #define CONFIG_SYS_INIT_SP_OFFSET \ 476 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 477 #define CONFIG_SYS_INIT_SP_ADDR \ 478 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 479 480 #ifdef CONFIG_SPL_BUILD 481 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 482 #else 483 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 484 #endif 485 486 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 487 488 /* 489 * Environment 490 */ 491 #define CONFIG_ENV_OVERWRITE 492 493 #if defined(CONFIG_SD_BOOT) 494 #define CONFIG_ENV_OFFSET 0x100000 495 #define CONFIG_ENV_IS_IN_MMC 496 #define CONFIG_SYS_MMC_ENV_DEV 0 497 #define CONFIG_ENV_SIZE 0x20000 498 #elif defined(CONFIG_QSPI_BOOT) 499 #define CONFIG_ENV_IS_IN_SPI_FLASH 500 #define CONFIG_ENV_SIZE 0x2000 501 #define CONFIG_ENV_OFFSET 0x100000 502 #define CONFIG_ENV_SECT_SIZE 0x10000 503 #else 504 #define CONFIG_ENV_IS_IN_FLASH 505 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 506 #define CONFIG_ENV_SIZE 0x20000 507 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 508 #endif 509 510 #define CONFIG_MISC_INIT_R 511 512 /* Hash command with SHA acceleration supported in hardware */ 513 #ifdef CONFIG_FSL_CAAM 514 #define CONFIG_CMD_HASH 515 #define CONFIG_SHA_HW_ACCEL 516 #endif 517 518 #include <asm/fsl_secure_boot.h> 519 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 520 521 #endif 522