1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 #define CONFIG_LS1_DEEP_SLEEP 14 15 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 16 17 #define CONFIG_SYS_FSL_CLK 18 19 #define CONFIG_DISPLAY_CPUINFO 20 #define CONFIG_DISPLAY_BOARDINFO 21 22 #define CONFIG_SKIP_LOWLEVEL_INIT 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_DEEP_SLEEP 25 #ifdef CONFIG_DEEP_SLEEP 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * USB 39 */ 40 41 /* 42 * EHCI Support - disbaled by default as 43 * there is no signal coming out of soc on 44 * this board for this controller. However, 45 * the silicon still has this controller, 46 * and anyone can use this controller by 47 * taking signals out on their board. 48 */ 49 50 /*#define CONFIG_HAS_FSL_DR_USB*/ 51 52 #ifdef CONFIG_HAS_FSL_DR_USB 53 #define CONFIG_USB_EHCI 54 #define CONFIG_USB_EHCI_FSL 55 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 56 #endif 57 58 /* XHCI Support - enabled by default */ 59 #define CONFIG_HAS_FSL_XHCI_USB 60 61 #ifdef CONFIG_HAS_FSL_XHCI_USB 62 #define CONFIG_USB_XHCI_FSL 63 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 64 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 65 #endif 66 67 /* 68 * Generic Timer Definitions 69 */ 70 #define GENERIC_TIMER_CLK 12500000 71 72 #define CONFIG_SYS_CLK_FREQ 100000000 73 #define CONFIG_DDR_CLK_FREQ 100000000 74 75 #define DDR_SDRAM_CFG 0x470c0008 76 #define DDR_CS0_BNDS 0x008000bf 77 #define DDR_CS0_CONFIG 0x80014302 78 #define DDR_TIMING_CFG_0 0x50550004 79 #define DDR_TIMING_CFG_1 0xbcb38c56 80 #define DDR_TIMING_CFG_2 0x0040d120 81 #define DDR_TIMING_CFG_3 0x010e1000 82 #define DDR_TIMING_CFG_4 0x00000001 83 #define DDR_TIMING_CFG_5 0x03401400 84 #define DDR_SDRAM_CFG_2 0x00401010 85 #define DDR_SDRAM_MODE 0x00061c60 86 #define DDR_SDRAM_MODE_2 0x00180000 87 #define DDR_SDRAM_INTERVAL 0x18600618 88 #define DDR_DDR_WRLVL_CNTL 0x8655f605 89 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 90 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 91 #define DDR_DDR_CDR1 0x80040000 92 #define DDR_DDR_CDR2 0x00000001 93 #define DDR_SDRAM_CLK_CNTL 0x02000000 94 #define DDR_DDR_ZQ_CNTL 0x89080600 95 #define DDR_CS0_CONFIG_2 0 96 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 97 #define SDRAM_CFG2_D_INIT 0x00000010 98 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 99 #define SDRAM_CFG2_FRC_SR 0x80000000 100 #define SDRAM_CFG_BI 0x00000001 101 102 #ifdef CONFIG_RAMBOOT_PBL 103 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 104 #endif 105 106 #ifdef CONFIG_SD_BOOT 107 #ifdef CONFIG_SD_BOOT_QSPI 108 #define CONFIG_SYS_FSL_PBL_RCW \ 109 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 110 #else 111 #define CONFIG_SYS_FSL_PBL_RCW \ 112 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 113 #endif 114 #define CONFIG_SPL_FRAMEWORK 115 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 116 #define CONFIG_SPL_LIBCOMMON_SUPPORT 117 #define CONFIG_SPL_LIBGENERIC_SUPPORT 118 #define CONFIG_SPL_ENV_SUPPORT 119 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 120 #define CONFIG_SPL_I2C_SUPPORT 121 #define CONFIG_SPL_WATCHDOG_SUPPORT 122 #define CONFIG_SPL_SERIAL_SUPPORT 123 #define CONFIG_SPL_MMC_SUPPORT 124 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 125 126 #ifdef CONFIG_SECURE_BOOT 127 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 128 /* 129 * HDR would be appended at end of image and copied to DDR along 130 * with U-Boot image. 131 */ 132 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 133 (CONFIG_U_BOOT_HDR_SIZE / 512) 134 #else 135 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 136 #endif /* ifdef CONFIG_SECURE_BOOT */ 137 138 #define CONFIG_SPL_TEXT_BASE 0x10000000 139 #define CONFIG_SPL_MAX_SIZE 0x1a000 140 #define CONFIG_SPL_STACK 0x1001d000 141 #define CONFIG_SPL_PAD_TO 0x1c000 142 #define CONFIG_SYS_TEXT_BASE 0x82000000 143 144 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 145 CONFIG_SYS_MONITOR_LEN) 146 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 147 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 148 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 149 150 #ifdef CONFIG_U_BOOT_HDR_SIZE 151 /* 152 * HDR would be appended at end of image and copied to DDR along 153 * with U-Boot image. Here u-boot max. size is 512K. So if binary 154 * size increases then increase this size in case of secure boot as 155 * it uses raw u-boot image instead of fit image. 156 */ 157 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 158 #else 159 #define CONFIG_SYS_MONITOR_LEN 0x80000 160 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 161 #endif 162 163 #ifdef CONFIG_QSPI_BOOT 164 #define CONFIG_SYS_TEXT_BASE 0x40010000 165 #endif 166 167 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 168 #define CONFIG_SYS_NO_FLASH 169 #endif 170 171 #ifndef CONFIG_SYS_TEXT_BASE 172 #define CONFIG_SYS_TEXT_BASE 0x60100000 173 #endif 174 175 #define CONFIG_NR_DRAM_BANKS 1 176 #define PHYS_SDRAM 0x80000000 177 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 178 179 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 180 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 181 182 #define CONFIG_SYS_HAS_SERDES 183 184 #define CONFIG_FSL_CAAM /* Enable CAAM */ 185 186 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 187 !defined(CONFIG_QSPI_BOOT) 188 #define CONFIG_U_QE 189 #endif 190 191 /* 192 * IFC Definitions 193 */ 194 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 195 #define CONFIG_FSL_IFC 196 #define CONFIG_SYS_FLASH_BASE 0x60000000 197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 198 199 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 200 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 201 CSPR_PORT_SIZE_16 | \ 202 CSPR_MSEL_NOR | \ 203 CSPR_V) 204 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 205 206 /* NOR Flash Timing Params */ 207 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 208 CSOR_NOR_TRHZ_80) 209 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 210 FTIM0_NOR_TEADC(0x5) | \ 211 FTIM0_NOR_TAVDS(0x0) | \ 212 FTIM0_NOR_TEAHC(0x5)) 213 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 214 FTIM1_NOR_TRAD_NOR(0x1A) | \ 215 FTIM1_NOR_TSEQRAD_NOR(0x13)) 216 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 217 FTIM2_NOR_TCH(0x4) | \ 218 FTIM2_NOR_TWP(0x1c) | \ 219 FTIM2_NOR_TWPH(0x0e)) 220 #define CONFIG_SYS_NOR_FTIM3 0 221 222 #define CONFIG_FLASH_CFI_DRIVER 223 #define CONFIG_SYS_FLASH_CFI 224 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 225 #define CONFIG_SYS_FLASH_QUIET_TEST 226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 232 233 #define CONFIG_SYS_FLASH_EMPTY_INFO 234 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 235 236 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 237 #define CONFIG_SYS_WRITE_SWAPPED_DATA 238 #endif 239 240 /* CPLD */ 241 242 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 243 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 244 245 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 246 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 247 CSPR_PORT_SIZE_8 | \ 248 CSPR_MSEL_GPCM | \ 249 CSPR_V) 250 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 251 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 252 CSOR_NOR_NOR_MODE_AVD_NOR | \ 253 CSOR_NOR_TRHZ_80) 254 255 /* CPLD Timing parameters for IFC GPCM */ 256 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 257 FTIM0_GPCM_TEADC(0xf) | \ 258 FTIM0_GPCM_TEAHC(0xf)) 259 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 260 FTIM1_GPCM_TRAD(0x3f)) 261 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 262 FTIM2_GPCM_TCH(0xf) | \ 263 FTIM2_GPCM_TWP(0xff)) 264 #define CONFIG_SYS_FPGA_FTIM3 0x0 265 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 266 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 267 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 268 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 269 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 270 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 271 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 272 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 273 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 274 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 275 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 276 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 277 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 278 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 279 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 280 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 281 282 /* 283 * Serial Port 284 */ 285 #ifdef CONFIG_LPUART 286 #define CONFIG_LPUART_32B_REG 287 #else 288 #define CONFIG_CONS_INDEX 1 289 #define CONFIG_SYS_NS16550_SERIAL 290 #ifndef CONFIG_DM_SERIAL 291 #define CONFIG_SYS_NS16550_REG_SIZE 1 292 #endif 293 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 294 #endif 295 296 #define CONFIG_BAUDRATE 115200 297 298 /* 299 * I2C 300 */ 301 #define CONFIG_SYS_I2C 302 #define CONFIG_SYS_I2C_MXC 303 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 304 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 305 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 306 307 /* EEPROM */ 308 #define CONFIG_ID_EEPROM 309 #define CONFIG_SYS_I2C_EEPROM_NXID 310 #define CONFIG_SYS_EEPROM_BUS_NUM 1 311 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 312 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 315 316 /* 317 * MMC 318 */ 319 #define CONFIG_MMC 320 #define CONFIG_FSL_ESDHC 321 #define CONFIG_GENERIC_MMC 322 323 #define CONFIG_DOS_PARTITION 324 325 /* SPI */ 326 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 327 /* QSPI */ 328 #define QSPI0_AMBA_BASE 0x40000000 329 #define FSL_QSPI_FLASH_SIZE (1 << 24) 330 #define FSL_QSPI_FLASH_NUM 2 331 332 /* DSPI */ 333 #endif 334 335 /* DM SPI */ 336 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 337 #define CONFIG_DM_SPI_FLASH 338 #endif 339 340 /* 341 * Video 342 */ 343 #define CONFIG_FSL_DCU_FB 344 345 #ifdef CONFIG_FSL_DCU_FB 346 #define CONFIG_VIDEO 347 #define CONFIG_CMD_BMP 348 #define CONFIG_CFB_CONSOLE 349 #define CONFIG_VGA_AS_SINGLE_DEVICE 350 #define CONFIG_VIDEO_LOGO 351 #define CONFIG_VIDEO_BMP_LOGO 352 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 353 354 #define CONFIG_FSL_DCU_SII9022A 355 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 356 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 357 #endif 358 359 /* 360 * eTSEC 361 */ 362 #define CONFIG_TSEC_ENET 363 364 #ifdef CONFIG_TSEC_ENET 365 #define CONFIG_MII 366 #define CONFIG_MII_DEFAULT_TSEC 1 367 #define CONFIG_TSEC1 1 368 #define CONFIG_TSEC1_NAME "eTSEC1" 369 #define CONFIG_TSEC2 1 370 #define CONFIG_TSEC2_NAME "eTSEC2" 371 #define CONFIG_TSEC3 1 372 #define CONFIG_TSEC3_NAME "eTSEC3" 373 374 #define TSEC1_PHY_ADDR 2 375 #define TSEC2_PHY_ADDR 0 376 #define TSEC3_PHY_ADDR 1 377 378 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 379 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 380 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 381 382 #define TSEC1_PHYIDX 0 383 #define TSEC2_PHYIDX 0 384 #define TSEC3_PHYIDX 0 385 386 #define CONFIG_ETHPRIME "eTSEC1" 387 388 #define CONFIG_PHY_GIGE 389 #define CONFIG_PHYLIB 390 #define CONFIG_PHY_ATHEROS 391 392 #define CONFIG_HAS_ETH0 393 #define CONFIG_HAS_ETH1 394 #define CONFIG_HAS_ETH2 395 #endif 396 397 /* PCIe */ 398 #define CONFIG_PCI /* Enable PCI/PCIE */ 399 #define CONFIG_PCIE1 /* PCIE controller 1 */ 400 #define CONFIG_PCIE2 /* PCIE controller 2 */ 401 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 402 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 403 404 #define CONFIG_SYS_PCI_64BIT 405 406 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 407 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 408 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 409 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 410 411 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 412 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 413 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 414 415 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 416 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 417 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 418 419 #ifdef CONFIG_PCI 420 #define CONFIG_PCI_PNP 421 #define CONFIG_PCI_SCAN_SHOW 422 #define CONFIG_CMD_PCI 423 #endif 424 425 #define CONFIG_CMDLINE_TAG 426 #define CONFIG_CMDLINE_EDITING 427 428 #define CONFIG_ARMV7_NONSEC 429 #define CONFIG_ARMV7_VIRT 430 #define CONFIG_PEN_ADDR_BIG_ENDIAN 431 #define CONFIG_LAYERSCAPE_NS_ACCESS 432 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 433 #define CONFIG_TIMER_CLK_FREQ 12500000 434 435 #define CONFIG_HWCONFIG 436 #define HWCONFIG_BUFFER_SIZE 256 437 438 #define CONFIG_FSL_DEVICE_DISABLE 439 440 441 #ifdef CONFIG_LPUART 442 #define CONFIG_EXTRA_ENV_SETTINGS \ 443 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 444 "initrd_high=0xffffffff\0" \ 445 "fdt_high=0xffffffff\0" 446 #else 447 #define CONFIG_EXTRA_ENV_SETTINGS \ 448 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 449 "initrd_high=0xffffffff\0" \ 450 "fdt_high=0xffffffff\0" 451 #endif 452 453 /* 454 * Miscellaneous configurable options 455 */ 456 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 457 #define CONFIG_AUTO_COMPLETE 458 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 459 #define CONFIG_SYS_PBSIZE \ 460 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 461 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 463 464 #define CONFIG_SYS_MEMTEST_START 0x80000000 465 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 466 467 #define CONFIG_SYS_LOAD_ADDR 0x82000000 468 469 #define CONFIG_LS102XA_STREAM_ID 470 471 /* 472 * Stack sizes 473 * The stack sizes are set up in start.S using the settings below 474 */ 475 #define CONFIG_STACKSIZE (30 * 1024) 476 477 #define CONFIG_SYS_INIT_SP_OFFSET \ 478 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_ADDR \ 480 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 481 482 #ifdef CONFIG_SPL_BUILD 483 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 484 #else 485 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 486 #endif 487 488 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 489 490 /* 491 * Environment 492 */ 493 #define CONFIG_ENV_OVERWRITE 494 495 #if defined(CONFIG_SD_BOOT) 496 #define CONFIG_ENV_OFFSET 0x100000 497 #define CONFIG_ENV_IS_IN_MMC 498 #define CONFIG_SYS_MMC_ENV_DEV 0 499 #define CONFIG_ENV_SIZE 0x20000 500 #elif defined(CONFIG_QSPI_BOOT) 501 #define CONFIG_ENV_IS_IN_SPI_FLASH 502 #define CONFIG_ENV_SIZE 0x2000 503 #define CONFIG_ENV_OFFSET 0x100000 504 #define CONFIG_ENV_SECT_SIZE 0x10000 505 #else 506 #define CONFIG_ENV_IS_IN_FLASH 507 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 508 #define CONFIG_ENV_SIZE 0x20000 509 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 510 #endif 511 512 #define CONFIG_MISC_INIT_R 513 514 /* Hash command with SHA acceleration supported in hardware */ 515 #ifdef CONFIG_FSL_CAAM 516 #define CONFIG_CMD_HASH 517 #define CONFIG_SHA_HW_ACCEL 518 #endif 519 520 #include <asm/fsl_secure_boot.h> 521 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 522 523 #endif 524