1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 #define CONFIG_DEEP_SLEEP 22 #ifdef CONFIG_DEEP_SLEEP 23 #define CONFIG_SILENT_CONSOLE 24 #endif 25 26 /* 27 * Size of malloc() pool 28 */ 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 30 31 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 32 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 33 34 /* 35 * USB 36 */ 37 38 /* 39 * EHCI Support - disbaled by default as 40 * there is no signal coming out of soc on 41 * this board for this controller. However, 42 * the silicon still has this controller, 43 * and anyone can use this controller by 44 * taking signals out on their board. 45 */ 46 47 /*#define CONFIG_HAS_FSL_DR_USB*/ 48 49 #ifdef CONFIG_HAS_FSL_DR_USB 50 #define CONFIG_USB_EHCI 51 #define CONFIG_USB_EHCI_FSL 52 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 53 #endif 54 55 /* XHCI Support - enabled by default */ 56 #define CONFIG_HAS_FSL_XHCI_USB 57 58 #ifdef CONFIG_HAS_FSL_XHCI_USB 59 #define CONFIG_USB_XHCI_FSL 60 #define CONFIG_USB_XHCI_DWC3 61 #define CONFIG_USB_XHCI 62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 64 #endif 65 66 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 67 #define CONFIG_USB_STORAGE 68 #define CONFIG_CMD_EXT2 69 #endif 70 71 /* 72 * Generic Timer Definitions 73 */ 74 #define GENERIC_TIMER_CLK 12500000 75 76 #define CONFIG_SYS_CLK_FREQ 100000000 77 #define CONFIG_DDR_CLK_FREQ 100000000 78 79 #define DDR_SDRAM_CFG 0x470c0008 80 #define DDR_CS0_BNDS 0x008000bf 81 #define DDR_CS0_CONFIG 0x80014302 82 #define DDR_TIMING_CFG_0 0x50550004 83 #define DDR_TIMING_CFG_1 0xbcb38c56 84 #define DDR_TIMING_CFG_2 0x0040d120 85 #define DDR_TIMING_CFG_3 0x010e1000 86 #define DDR_TIMING_CFG_4 0x00000001 87 #define DDR_TIMING_CFG_5 0x03401400 88 #define DDR_SDRAM_CFG_2 0x00401010 89 #define DDR_SDRAM_MODE 0x00061c60 90 #define DDR_SDRAM_MODE_2 0x00180000 91 #define DDR_SDRAM_INTERVAL 0x18600618 92 #define DDR_DDR_WRLVL_CNTL 0x8655f605 93 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 94 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 95 #define DDR_DDR_CDR1 0x80040000 96 #define DDR_DDR_CDR2 0x00000001 97 #define DDR_SDRAM_CLK_CNTL 0x02000000 98 #define DDR_DDR_ZQ_CNTL 0x89080600 99 #define DDR_CS0_CONFIG_2 0 100 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 101 #define SDRAM_CFG2_D_INIT 0x00000010 102 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 103 #define SDRAM_CFG2_FRC_SR 0x80000000 104 #define SDRAM_CFG_BI 0x00000001 105 106 #ifdef CONFIG_RAMBOOT_PBL 107 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 108 #endif 109 110 #ifdef CONFIG_SD_BOOT 111 #ifdef CONFIG_SD_BOOT_QSPI 112 #define CONFIG_SYS_FSL_PBL_RCW \ 113 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 114 #else 115 #define CONFIG_SYS_FSL_PBL_RCW \ 116 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 117 #endif 118 #define CONFIG_SPL_FRAMEWORK 119 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 120 #define CONFIG_SPL_LIBCOMMON_SUPPORT 121 #define CONFIG_SPL_LIBGENERIC_SUPPORT 122 #define CONFIG_SPL_ENV_SUPPORT 123 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 124 #define CONFIG_SPL_I2C_SUPPORT 125 #define CONFIG_SPL_WATCHDOG_SUPPORT 126 #define CONFIG_SPL_SERIAL_SUPPORT 127 #define CONFIG_SPL_MMC_SUPPORT 128 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 129 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 130 131 #define CONFIG_SPL_TEXT_BASE 0x10000000 132 #define CONFIG_SPL_MAX_SIZE 0x1a000 133 #define CONFIG_SPL_STACK 0x1001d000 134 #define CONFIG_SPL_PAD_TO 0x1c000 135 #define CONFIG_SYS_TEXT_BASE 0x82000000 136 137 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 138 CONFIG_SYS_MONITOR_LEN) 139 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 140 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 141 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 142 #define CONFIG_SYS_MONITOR_LEN 0x80000 143 #endif 144 145 #ifdef CONFIG_QSPI_BOOT 146 #define CONFIG_SYS_TEXT_BASE 0x40010000 147 #endif 148 149 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 150 #define CONFIG_SYS_NO_FLASH 151 #endif 152 153 #ifndef CONFIG_SYS_TEXT_BASE 154 #define CONFIG_SYS_TEXT_BASE 0x60100000 155 #endif 156 157 #define CONFIG_NR_DRAM_BANKS 1 158 #define PHYS_SDRAM 0x80000000 159 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 160 161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 163 164 #define CONFIG_SYS_HAS_SERDES 165 166 #define CONFIG_FSL_CAAM /* Enable CAAM */ 167 168 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 169 !defined(CONFIG_QSPI_BOOT) 170 #define CONFIG_U_QE 171 #endif 172 173 /* 174 * IFC Definitions 175 */ 176 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 177 #define CONFIG_FSL_IFC 178 #define CONFIG_SYS_FLASH_BASE 0x60000000 179 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 180 181 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 182 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 183 CSPR_PORT_SIZE_16 | \ 184 CSPR_MSEL_NOR | \ 185 CSPR_V) 186 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 187 188 /* NOR Flash Timing Params */ 189 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 190 CSOR_NOR_TRHZ_80) 191 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 192 FTIM0_NOR_TEADC(0x5) | \ 193 FTIM0_NOR_TAVDS(0x0) | \ 194 FTIM0_NOR_TEAHC(0x5)) 195 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 196 FTIM1_NOR_TRAD_NOR(0x1A) | \ 197 FTIM1_NOR_TSEQRAD_NOR(0x13)) 198 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 199 FTIM2_NOR_TCH(0x4) | \ 200 FTIM2_NOR_TWP(0x1c) | \ 201 FTIM2_NOR_TWPH(0x0e)) 202 #define CONFIG_SYS_NOR_FTIM3 0 203 204 #define CONFIG_FLASH_CFI_DRIVER 205 #define CONFIG_SYS_FLASH_CFI 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 207 #define CONFIG_SYS_FLASH_QUIET_TEST 208 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 209 210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 214 215 #define CONFIG_SYS_FLASH_EMPTY_INFO 216 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 217 218 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 219 #define CONFIG_SYS_WRITE_SWAPPED_DATA 220 #endif 221 222 /* CPLD */ 223 224 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 225 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 226 227 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 228 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 229 CSPR_PORT_SIZE_8 | \ 230 CSPR_MSEL_GPCM | \ 231 CSPR_V) 232 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 233 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 234 CSOR_NOR_NOR_MODE_AVD_NOR | \ 235 CSOR_NOR_TRHZ_80) 236 237 /* CPLD Timing parameters for IFC GPCM */ 238 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 239 FTIM0_GPCM_TEADC(0xf) | \ 240 FTIM0_GPCM_TEAHC(0xf)) 241 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 242 FTIM1_GPCM_TRAD(0x3f)) 243 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 244 FTIM2_GPCM_TCH(0xf) | \ 245 FTIM2_GPCM_TWP(0xff)) 246 #define CONFIG_SYS_FPGA_FTIM3 0x0 247 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 255 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 258 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 259 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 260 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 261 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 262 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 263 264 /* 265 * Serial Port 266 */ 267 #ifdef CONFIG_LPUART 268 #define CONFIG_LPUART_32B_REG 269 #else 270 #define CONFIG_CONS_INDEX 1 271 #define CONFIG_SYS_NS16550_SERIAL 272 #ifndef CONFIG_DM_SERIAL 273 #define CONFIG_SYS_NS16550_REG_SIZE 1 274 #endif 275 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 276 #endif 277 278 #define CONFIG_BAUDRATE 115200 279 280 /* 281 * I2C 282 */ 283 #define CONFIG_SYS_I2C 284 #define CONFIG_SYS_I2C_MXC 285 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 286 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 287 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 288 289 /* EEPROM */ 290 #define CONFIG_ID_EEPROM 291 #define CONFIG_SYS_I2C_EEPROM_NXID 292 #define CONFIG_SYS_EEPROM_BUS_NUM 1 293 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 294 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 295 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 296 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 297 298 /* 299 * MMC 300 */ 301 #define CONFIG_MMC 302 #define CONFIG_CMD_MMC 303 #define CONFIG_FSL_ESDHC 304 #define CONFIG_GENERIC_MMC 305 306 #define CONFIG_CMD_FAT 307 #define CONFIG_DOS_PARTITION 308 309 /* SPI */ 310 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 311 /* QSPI */ 312 #define QSPI0_AMBA_BASE 0x40000000 313 #define FSL_QSPI_FLASH_SIZE (1 << 24) 314 #define FSL_QSPI_FLASH_NUM 2 315 316 /* DSPI */ 317 #endif 318 319 /* DM SPI */ 320 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 321 #define CONFIG_DM_SPI_FLASH 322 #endif 323 324 /* 325 * Video 326 */ 327 #define CONFIG_FSL_DCU_FB 328 329 #ifdef CONFIG_FSL_DCU_FB 330 #define CONFIG_VIDEO 331 #define CONFIG_CMD_BMP 332 #define CONFIG_CFB_CONSOLE 333 #define CONFIG_VGA_AS_SINGLE_DEVICE 334 #define CONFIG_VIDEO_LOGO 335 #define CONFIG_VIDEO_BMP_LOGO 336 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 337 338 #define CONFIG_FSL_DCU_SII9022A 339 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 340 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 341 #endif 342 343 /* 344 * eTSEC 345 */ 346 #define CONFIG_TSEC_ENET 347 348 #ifdef CONFIG_TSEC_ENET 349 #define CONFIG_MII 350 #define CONFIG_MII_DEFAULT_TSEC 1 351 #define CONFIG_TSEC1 1 352 #define CONFIG_TSEC1_NAME "eTSEC1" 353 #define CONFIG_TSEC2 1 354 #define CONFIG_TSEC2_NAME "eTSEC2" 355 #define CONFIG_TSEC3 1 356 #define CONFIG_TSEC3_NAME "eTSEC3" 357 358 #define TSEC1_PHY_ADDR 2 359 #define TSEC2_PHY_ADDR 0 360 #define TSEC3_PHY_ADDR 1 361 362 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 363 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 364 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 365 366 #define TSEC1_PHYIDX 0 367 #define TSEC2_PHYIDX 0 368 #define TSEC3_PHYIDX 0 369 370 #define CONFIG_ETHPRIME "eTSEC1" 371 372 #define CONFIG_PHY_GIGE 373 #define CONFIG_PHYLIB 374 #define CONFIG_PHY_ATHEROS 375 376 #define CONFIG_HAS_ETH0 377 #define CONFIG_HAS_ETH1 378 #define CONFIG_HAS_ETH2 379 #endif 380 381 /* PCIe */ 382 #define CONFIG_PCI /* Enable PCI/PCIE */ 383 #define CONFIG_PCIE1 /* PCIE controler 1 */ 384 #define CONFIG_PCIE2 /* PCIE controler 2 */ 385 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 386 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 387 388 #define CONFIG_SYS_PCI_64BIT 389 390 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 391 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 392 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 393 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 394 395 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 396 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 397 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 398 399 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 400 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 401 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 402 403 #ifdef CONFIG_PCI 404 #define CONFIG_PCI_PNP 405 #define CONFIG_PCI_SCAN_SHOW 406 #define CONFIG_CMD_PCI 407 #endif 408 409 #define CONFIG_CMD_MII 410 411 #define CONFIG_CMDLINE_TAG 412 #define CONFIG_CMDLINE_EDITING 413 414 #define CONFIG_ARMV7_NONSEC 415 #define CONFIG_ARMV7_VIRT 416 #define CONFIG_PEN_ADDR_BIG_ENDIAN 417 #define CONFIG_LAYERSCAPE_NS_ACCESS 418 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 419 #define CONFIG_TIMER_CLK_FREQ 12500000 420 421 #define CONFIG_HWCONFIG 422 #define HWCONFIG_BUFFER_SIZE 256 423 424 #define CONFIG_FSL_DEVICE_DISABLE 425 426 #define CONFIG_BOOTDELAY 3 427 428 #ifdef CONFIG_LPUART 429 #define CONFIG_EXTRA_ENV_SETTINGS \ 430 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 431 "initrd_high=0xffffffff\0" \ 432 "fdt_high=0xffffffff\0" 433 #else 434 #define CONFIG_EXTRA_ENV_SETTINGS \ 435 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 436 "initrd_high=0xffffffff\0" \ 437 "fdt_high=0xffffffff\0" 438 #endif 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 444 #define CONFIG_AUTO_COMPLETE 445 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 446 #define CONFIG_SYS_PBSIZE \ 447 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 448 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 449 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 450 451 #define CONFIG_CMD_GREPENV 452 #define CONFIG_SYS_MEMTEST_START 0x80000000 453 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 454 455 #define CONFIG_SYS_LOAD_ADDR 0x82000000 456 457 #define CONFIG_LS102XA_STREAM_ID 458 459 /* 460 * Stack sizes 461 * The stack sizes are set up in start.S using the settings below 462 */ 463 #define CONFIG_STACKSIZE (30 * 1024) 464 465 #define CONFIG_SYS_INIT_SP_OFFSET \ 466 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 467 #define CONFIG_SYS_INIT_SP_ADDR \ 468 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 469 470 #ifdef CONFIG_SPL_BUILD 471 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 472 #else 473 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 474 #endif 475 476 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 477 478 /* 479 * Environment 480 */ 481 #define CONFIG_ENV_OVERWRITE 482 483 #if defined(CONFIG_SD_BOOT) 484 #define CONFIG_ENV_OFFSET 0x100000 485 #define CONFIG_ENV_IS_IN_MMC 486 #define CONFIG_SYS_MMC_ENV_DEV 0 487 #define CONFIG_ENV_SIZE 0x20000 488 #elif defined(CONFIG_QSPI_BOOT) 489 #define CONFIG_ENV_IS_IN_SPI_FLASH 490 #define CONFIG_ENV_SIZE 0x2000 491 #define CONFIG_ENV_OFFSET 0x100000 492 #define CONFIG_ENV_SECT_SIZE 0x10000 493 #else 494 #define CONFIG_ENV_IS_IN_FLASH 495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 496 #define CONFIG_ENV_SIZE 0x20000 497 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 498 #endif 499 500 #define CONFIG_CMD_BOOTZ 501 502 #define CONFIG_MISC_INIT_R 503 504 /* Hash command with SHA acceleration supported in hardware */ 505 #ifdef CONFIG_FSL_CAAM 506 #define CONFIG_CMD_HASH 507 #define CONFIG_SHA_HW_ACCEL 508 #endif 509 510 #include <asm/fsl_secure_boot.h> 511 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 512 513 #endif 514