1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SPL_LIBCOMMON_SUPPORT 71 #define CONFIG_SPL_LIBGENERIC_SUPPORT 72 #define CONFIG_SPL_ENV_SUPPORT 73 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 74 #define CONFIG_SPL_I2C_SUPPORT 75 #define CONFIG_SPL_WATCHDOG_SUPPORT 76 #define CONFIG_SPL_SERIAL_SUPPORT 77 #define CONFIG_SPL_MMC_SUPPORT 78 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 79 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 80 81 #define CONFIG_SPL_TEXT_BASE 0x10000000 82 #define CONFIG_SPL_MAX_SIZE 0x1a000 83 #define CONFIG_SPL_STACK 0x1001d000 84 #define CONFIG_SPL_PAD_TO 0x1c000 85 #define CONFIG_SYS_TEXT_BASE 0x82000000 86 87 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 88 CONFIG_SYS_MONITOR_LEN) 89 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 90 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 91 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 92 #define CONFIG_SYS_MONITOR_LEN 0xc0000 93 #endif 94 95 #ifdef CONFIG_QSPI_BOOT 96 #define CONFIG_SYS_TEXT_BASE 0x40010000 97 #endif 98 99 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 100 #define CONFIG_SYS_NO_FLASH 101 #endif 102 103 #ifdef CONFIG_NAND_BOOT 104 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 105 #define CONFIG_SPL_FRAMEWORK 106 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 107 #define CONFIG_SPL_LIBCOMMON_SUPPORT 108 #define CONFIG_SPL_LIBGENERIC_SUPPORT 109 #define CONFIG_SPL_ENV_SUPPORT 110 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 111 #define CONFIG_SPL_I2C_SUPPORT 112 #define CONFIG_SPL_WATCHDOG_SUPPORT 113 #define CONFIG_SPL_SERIAL_SUPPORT 114 #define CONFIG_SPL_NAND_SUPPORT 115 116 #define CONFIG_SPL_TEXT_BASE 0x10000000 117 #define CONFIG_SPL_MAX_SIZE 0x1a000 118 #define CONFIG_SPL_STACK 0x1001d000 119 #define CONFIG_SPL_PAD_TO 0x1c000 120 #define CONFIG_SYS_TEXT_BASE 0x82000000 121 122 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 123 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 124 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 125 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 126 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 127 128 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 129 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 130 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 131 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 132 #define CONFIG_SYS_MONITOR_LEN 0x80000 133 #endif 134 135 #ifndef CONFIG_SYS_TEXT_BASE 136 #define CONFIG_SYS_TEXT_BASE 0x60100000 137 #endif 138 139 #define CONFIG_NR_DRAM_BANKS 1 140 141 #define CONFIG_DDR_SPD 142 #define SPD_EEPROM_ADDRESS 0x51 143 #define CONFIG_SYS_SPD_BUS_NUM 0 144 145 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 146 #ifndef CONFIG_SYS_FSL_DDR4 147 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 148 #define CONFIG_SYS_DDR_RAW_TIMING 149 #endif 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 155 156 #define CONFIG_DDR_ECC 157 #ifdef CONFIG_DDR_ECC 158 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 159 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 160 #endif 161 162 #define CONFIG_SYS_HAS_SERDES 163 164 #define CONFIG_FSL_CAAM /* Enable CAAM */ 165 166 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 167 !defined(CONFIG_QSPI_BOOT) 168 #define CONFIG_U_QE 169 #endif 170 171 /* 172 * IFC Definitions 173 */ 174 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 175 #define CONFIG_FSL_IFC 176 #define CONFIG_SYS_FLASH_BASE 0x60000000 177 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 178 179 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 180 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 186 + 0x8000000) | \ 187 CSPR_PORT_SIZE_16 | \ 188 CSPR_MSEL_NOR | \ 189 CSPR_V) 190 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 191 192 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 193 CSOR_NOR_TRHZ_80) 194 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 195 FTIM0_NOR_TEADC(0x5) | \ 196 FTIM0_NOR_TEAHC(0x5)) 197 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 198 FTIM1_NOR_TRAD_NOR(0x1a) | \ 199 FTIM1_NOR_TSEQRAD_NOR(0x13)) 200 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 201 FTIM2_NOR_TCH(0x4) | \ 202 FTIM2_NOR_TWPH(0xe) | \ 203 FTIM2_NOR_TWP(0x1c)) 204 #define CONFIG_SYS_NOR_FTIM3 0 205 206 #define CONFIG_FLASH_CFI_DRIVER 207 #define CONFIG_SYS_FLASH_CFI 208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 209 #define CONFIG_SYS_FLASH_QUIET_TEST 210 #define CONFIG_FLASH_SHOW_PROGRESS 45 211 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 212 #define CONFIG_SYS_WRITE_SWAPPED_DATA 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 221 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 222 223 /* 224 * NAND Flash Definitions 225 */ 226 #define CONFIG_NAND_FSL_IFC 227 228 #define CONFIG_SYS_NAND_BASE 0x7e800000 229 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 230 231 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 232 233 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_NAND \ 236 | CSPR_V) 237 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 238 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 239 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 240 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 241 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 242 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 243 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 244 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 245 246 #define CONFIG_SYS_NAND_ONFI_DETECTION 247 248 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 249 FTIM0_NAND_TWP(0x18) | \ 250 FTIM0_NAND_TWCHT(0x7) | \ 251 FTIM0_NAND_TWH(0xa)) 252 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 253 FTIM1_NAND_TWBE(0x39) | \ 254 FTIM1_NAND_TRR(0xe) | \ 255 FTIM1_NAND_TRP(0x18)) 256 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 257 FTIM2_NAND_TREH(0xa) | \ 258 FTIM2_NAND_TWHRE(0x1e)) 259 #define CONFIG_SYS_NAND_FTIM3 0x0 260 261 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 262 #define CONFIG_SYS_MAX_NAND_DEVICE 1 263 #define CONFIG_CMD_NAND 264 265 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 266 #endif 267 268 /* 269 * QIXIS Definitions 270 */ 271 #define CONFIG_FSL_QIXIS 272 273 #ifdef CONFIG_FSL_QIXIS 274 #define QIXIS_BASE 0x7fb00000 275 #define QIXIS_BASE_PHYS QIXIS_BASE 276 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 277 #define QIXIS_LBMAP_SWITCH 6 278 #define QIXIS_LBMAP_MASK 0x0f 279 #define QIXIS_LBMAP_SHIFT 0 280 #define QIXIS_LBMAP_DFLTBANK 0x00 281 #define QIXIS_LBMAP_ALTBANK 0x04 282 #define QIXIS_PWR_CTL 0x21 283 #define QIXIS_PWR_CTL_POWEROFF 0x80 284 #define QIXIS_RST_CTL_RESET 0x44 285 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 286 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 287 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 288 289 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 290 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 291 CSPR_PORT_SIZE_8 | \ 292 CSPR_MSEL_GPCM | \ 293 CSPR_V) 294 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 295 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 296 CSOR_NOR_NOR_MODE_AVD_NOR | \ 297 CSOR_NOR_TRHZ_80) 298 299 /* 300 * QIXIS Timing parameters for IFC GPCM 301 */ 302 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 303 FTIM0_GPCM_TEADC(0xe) | \ 304 FTIM0_GPCM_TEAHC(0xe)) 305 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 306 FTIM1_GPCM_TRAD(0x1f)) 307 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 308 FTIM2_GPCM_TCH(0xe) | \ 309 FTIM2_GPCM_TWP(0xf0)) 310 #define CONFIG_SYS_FPGA_FTIM3 0x0 311 #endif 312 313 #if defined(CONFIG_NAND_BOOT) 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 339 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 340 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 341 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 342 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 343 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 344 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 345 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 346 #else 347 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 348 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 349 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 355 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 371 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 372 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 373 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 374 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 375 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 376 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 377 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 378 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 379 #endif 380 381 /* 382 * Serial Port 383 */ 384 #ifdef CONFIG_LPUART 385 #define CONFIG_LPUART_32B_REG 386 #else 387 #define CONFIG_CONS_INDEX 1 388 #define CONFIG_SYS_NS16550_SERIAL 389 #ifndef CONFIG_DM_SERIAL 390 #define CONFIG_SYS_NS16550_REG_SIZE 1 391 #endif 392 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 393 #endif 394 395 #define CONFIG_BAUDRATE 115200 396 397 /* 398 * I2C 399 */ 400 #define CONFIG_SYS_I2C 401 #define CONFIG_SYS_I2C_MXC 402 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 403 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 404 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 405 406 /* 407 * I2C bus multiplexer 408 */ 409 #define I2C_MUX_PCA_ADDR_PRI 0x77 410 #define I2C_MUX_CH_DEFAULT 0x8 411 #define I2C_MUX_CH_CH7301 0xC 412 413 /* 414 * MMC 415 */ 416 #define CONFIG_MMC 417 #define CONFIG_FSL_ESDHC 418 #define CONFIG_GENERIC_MMC 419 420 #define CONFIG_DOS_PARTITION 421 422 /* SPI */ 423 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 424 /* QSPI */ 425 #define QSPI0_AMBA_BASE 0x40000000 426 #define FSL_QSPI_FLASH_SIZE (1 << 24) 427 #define FSL_QSPI_FLASH_NUM 2 428 429 /* DSPI */ 430 431 /* DM SPI */ 432 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 433 #define CONFIG_DM_SPI_FLASH 434 #define CONFIG_SPI_FLASH_DATAFLASH 435 #endif 436 #endif 437 438 /* 439 * USB 440 */ 441 /* EHCI Support - disbaled by default */ 442 /*#define CONFIG_HAS_FSL_DR_USB*/ 443 444 #ifdef CONFIG_HAS_FSL_DR_USB 445 #define CONFIG_USB_EHCI 446 #define CONFIG_USB_EHCI_FSL 447 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 448 #endif 449 450 /*XHCI Support - enabled by default*/ 451 #define CONFIG_HAS_FSL_XHCI_USB 452 453 #ifdef CONFIG_HAS_FSL_XHCI_USB 454 #define CONFIG_USB_XHCI_FSL 455 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 456 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 457 #endif 458 459 /* 460 * Video 461 */ 462 #define CONFIG_FSL_DCU_FB 463 464 #ifdef CONFIG_FSL_DCU_FB 465 #define CONFIG_VIDEO 466 #define CONFIG_CMD_BMP 467 #define CONFIG_CFB_CONSOLE 468 #define CONFIG_VGA_AS_SINGLE_DEVICE 469 #define CONFIG_VIDEO_LOGO 470 #define CONFIG_VIDEO_BMP_LOGO 471 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 472 473 #define CONFIG_FSL_DIU_CH7301 474 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 475 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 476 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 477 #endif 478 479 /* 480 * eTSEC 481 */ 482 #define CONFIG_TSEC_ENET 483 484 #ifdef CONFIG_TSEC_ENET 485 #define CONFIG_MII 486 #define CONFIG_MII_DEFAULT_TSEC 3 487 #define CONFIG_TSEC1 1 488 #define CONFIG_TSEC1_NAME "eTSEC1" 489 #define CONFIG_TSEC2 1 490 #define CONFIG_TSEC2_NAME "eTSEC2" 491 #define CONFIG_TSEC3 1 492 #define CONFIG_TSEC3_NAME "eTSEC3" 493 494 #define TSEC1_PHY_ADDR 1 495 #define TSEC2_PHY_ADDR 2 496 #define TSEC3_PHY_ADDR 3 497 498 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 499 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501 502 #define TSEC1_PHYIDX 0 503 #define TSEC2_PHYIDX 0 504 #define TSEC3_PHYIDX 0 505 506 #define CONFIG_ETHPRIME "eTSEC1" 507 508 #define CONFIG_PHY_GIGE 509 #define CONFIG_PHYLIB 510 #define CONFIG_PHY_REALTEK 511 512 #define CONFIG_HAS_ETH0 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_HAS_ETH2 515 516 #define CONFIG_FSL_SGMII_RISER 1 517 #define SGMII_RISER_PHY_OFFSET 0x1b 518 519 #ifdef CONFIG_FSL_SGMII_RISER 520 #define CONFIG_SYS_TBIPA_VALUE 8 521 #endif 522 523 #endif 524 525 /* PCIe */ 526 #define CONFIG_PCI /* Enable PCI/PCIE */ 527 #define CONFIG_PCIE1 /* PCIE controller 1 */ 528 #define CONFIG_PCIE2 /* PCIE controller 2 */ 529 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 530 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 531 532 #define CONFIG_SYS_PCI_64BIT 533 534 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 535 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 536 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 537 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 538 539 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 540 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 541 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 542 543 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 544 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 545 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 546 547 #ifdef CONFIG_PCI 548 #define CONFIG_PCI_PNP 549 #define CONFIG_PCI_SCAN_SHOW 550 #define CONFIG_CMD_PCI 551 #endif 552 553 #define CONFIG_CMDLINE_TAG 554 #define CONFIG_CMDLINE_EDITING 555 556 #define CONFIG_ARMV7_NONSEC 557 #define CONFIG_ARMV7_VIRT 558 #define CONFIG_PEN_ADDR_BIG_ENDIAN 559 #define CONFIG_LAYERSCAPE_NS_ACCESS 560 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 561 #define CONFIG_TIMER_CLK_FREQ 12500000 562 563 #define CONFIG_HWCONFIG 564 #define HWCONFIG_BUFFER_SIZE 256 565 566 #define CONFIG_FSL_DEVICE_DISABLE 567 568 569 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 570 571 #ifdef CONFIG_LPUART 572 #define CONFIG_EXTRA_ENV_SETTINGS \ 573 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 574 "fdt_high=0xffffffff\0" \ 575 "initrd_high=0xffffffff\0" \ 576 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 577 #else 578 #define CONFIG_EXTRA_ENV_SETTINGS \ 579 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 580 "fdt_high=0xffffffff\0" \ 581 "initrd_high=0xffffffff\0" \ 582 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 583 #endif 584 585 /* 586 * Miscellaneous configurable options 587 */ 588 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 589 #define CONFIG_AUTO_COMPLETE 590 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 591 #define CONFIG_SYS_PBSIZE \ 592 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 593 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 594 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 595 596 #define CONFIG_SYS_MEMTEST_START 0x80000000 597 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 598 599 #define CONFIG_SYS_LOAD_ADDR 0x82000000 600 601 #define CONFIG_LS102XA_STREAM_ID 602 603 /* 604 * Stack sizes 605 * The stack sizes are set up in start.S using the settings below 606 */ 607 #define CONFIG_STACKSIZE (30 * 1024) 608 609 #define CONFIG_SYS_INIT_SP_OFFSET \ 610 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 611 #define CONFIG_SYS_INIT_SP_ADDR \ 612 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 613 614 #ifdef CONFIG_SPL_BUILD 615 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 616 #else 617 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 618 #endif 619 620 /* 621 * Environment 622 */ 623 #define CONFIG_ENV_OVERWRITE 624 625 #if defined(CONFIG_SD_BOOT) 626 #define CONFIG_ENV_OFFSET 0x100000 627 #define CONFIG_ENV_IS_IN_MMC 628 #define CONFIG_SYS_MMC_ENV_DEV 0 629 #define CONFIG_ENV_SIZE 0x2000 630 #elif defined(CONFIG_QSPI_BOOT) 631 #define CONFIG_ENV_IS_IN_SPI_FLASH 632 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 633 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 634 #define CONFIG_ENV_SECT_SIZE 0x10000 635 #elif defined(CONFIG_NAND_BOOT) 636 #define CONFIG_ENV_IS_IN_NAND 637 #define CONFIG_ENV_SIZE 0x2000 638 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 639 #else 640 #define CONFIG_ENV_IS_IN_FLASH 641 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 642 #define CONFIG_ENV_SIZE 0x2000 643 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 644 #endif 645 646 #define CONFIG_MISC_INIT_R 647 648 /* Hash command with SHA acceleration supported in hardware */ 649 #ifdef CONFIG_FSL_CAAM 650 #define CONFIG_CMD_HASH 651 #define CONFIG_SHA_HW_ACCEL 652 #endif 653 654 #include <asm/fsl_secure_boot.h> 655 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 656 657 #endif 658