1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 #define CONFIG_LS1_DEEP_SLEEP 14 15 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 16 17 #define CONFIG_SYS_FSL_CLK 18 19 #define CONFIG_DISPLAY_CPUINFO 20 #define CONFIG_DISPLAY_BOARDINFO 21 22 #define CONFIG_SKIP_LOWLEVEL_INIT 23 #define CONFIG_BOARD_EARLY_INIT_F 24 25 #define CONFIG_DEEP_SLEEP 26 #if defined(CONFIG_DEEP_SLEEP) 27 #define CONFIG_SILENT_CONSOLE 28 #endif 29 30 /* 31 * Size of malloc() pool 32 */ 33 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 34 35 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 36 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 37 38 /* 39 * Generic Timer Definitions 40 */ 41 #define GENERIC_TIMER_CLK 12500000 42 43 #ifndef __ASSEMBLY__ 44 unsigned long get_board_sys_clk(void); 45 unsigned long get_board_ddr_clk(void); 46 #endif 47 48 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 49 #define CONFIG_SYS_CLK_FREQ 100000000 50 #define CONFIG_DDR_CLK_FREQ 100000000 51 #define CONFIG_QIXIS_I2C_ACCESS 52 #else 53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 54 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 55 #endif 56 57 #ifdef CONFIG_RAMBOOT_PBL 58 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 59 #endif 60 61 #ifdef CONFIG_SD_BOOT 62 #ifdef CONFIG_SD_BOOT_QSPI 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 65 #else 66 #define CONFIG_SYS_FSL_PBL_RCW \ 67 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 68 #endif 69 #define CONFIG_SPL_FRAMEWORK 70 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 71 #define CONFIG_SPL_LIBCOMMON_SUPPORT 72 #define CONFIG_SPL_LIBGENERIC_SUPPORT 73 #define CONFIG_SPL_ENV_SUPPORT 74 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 75 #define CONFIG_SPL_I2C_SUPPORT 76 #define CONFIG_SPL_WATCHDOG_SUPPORT 77 #define CONFIG_SPL_SERIAL_SUPPORT 78 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 79 #define CONFIG_SPL_MMC_SUPPORT 80 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 81 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 82 83 #define CONFIG_SPL_TEXT_BASE 0x10000000 84 #define CONFIG_SPL_MAX_SIZE 0x1a000 85 #define CONFIG_SPL_STACK 0x1001d000 86 #define CONFIG_SPL_PAD_TO 0x1c000 87 #define CONFIG_SYS_TEXT_BASE 0x82000000 88 89 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 90 CONFIG_SYS_MONITOR_LEN) 91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 94 #define CONFIG_SYS_MONITOR_LEN 0xc0000 95 #endif 96 97 #ifdef CONFIG_QSPI_BOOT 98 #define CONFIG_SYS_TEXT_BASE 0x40010000 99 #endif 100 101 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 102 #define CONFIG_SYS_NO_FLASH 103 #endif 104 105 #ifdef CONFIG_NAND_BOOT 106 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 107 #define CONFIG_SPL_FRAMEWORK 108 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 109 #define CONFIG_SPL_LIBCOMMON_SUPPORT 110 #define CONFIG_SPL_LIBGENERIC_SUPPORT 111 #define CONFIG_SPL_ENV_SUPPORT 112 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 113 #define CONFIG_SPL_I2C_SUPPORT 114 #define CONFIG_SPL_WATCHDOG_SUPPORT 115 #define CONFIG_SPL_SERIAL_SUPPORT 116 #define CONFIG_SPL_NAND_SUPPORT 117 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 118 119 #define CONFIG_SPL_TEXT_BASE 0x10000000 120 #define CONFIG_SPL_MAX_SIZE 0x1a000 121 #define CONFIG_SPL_STACK 0x1001d000 122 #define CONFIG_SPL_PAD_TO 0x1c000 123 #define CONFIG_SYS_TEXT_BASE 0x82000000 124 125 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 126 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 127 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 128 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 129 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 130 131 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 132 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 133 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 134 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 135 #define CONFIG_SYS_MONITOR_LEN 0x80000 136 #endif 137 138 #ifndef CONFIG_SYS_TEXT_BASE 139 #define CONFIG_SYS_TEXT_BASE 0x60100000 140 #endif 141 142 #define CONFIG_NR_DRAM_BANKS 1 143 144 #define CONFIG_DDR_SPD 145 #define SPD_EEPROM_ADDRESS 0x51 146 #define CONFIG_SYS_SPD_BUS_NUM 0 147 148 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 149 #ifndef CONFIG_SYS_FSL_DDR4 150 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 151 #define CONFIG_SYS_DDR_RAW_TIMING 152 #endif 153 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 154 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 155 156 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 157 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 158 159 #define CONFIG_DDR_ECC 160 #ifdef CONFIG_DDR_ECC 161 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 162 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 163 #endif 164 165 #define CONFIG_SYS_HAS_SERDES 166 167 #define CONFIG_FSL_CAAM /* Enable CAAM */ 168 169 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 170 !defined(CONFIG_QSPI_BOOT) 171 #define CONFIG_U_QE 172 #endif 173 174 /* 175 * IFC Definitions 176 */ 177 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 178 #define CONFIG_FSL_IFC 179 #define CONFIG_SYS_FLASH_BASE 0x60000000 180 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 181 182 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 183 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 184 CSPR_PORT_SIZE_16 | \ 185 CSPR_MSEL_NOR | \ 186 CSPR_V) 187 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 188 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 189 + 0x8000000) | \ 190 CSPR_PORT_SIZE_16 | \ 191 CSPR_MSEL_NOR | \ 192 CSPR_V) 193 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 194 195 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 196 CSOR_NOR_TRHZ_80) 197 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 198 FTIM0_NOR_TEADC(0x5) | \ 199 FTIM0_NOR_TEAHC(0x5)) 200 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 201 FTIM1_NOR_TRAD_NOR(0x1a) | \ 202 FTIM1_NOR_TSEQRAD_NOR(0x13)) 203 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 204 FTIM2_NOR_TCH(0x4) | \ 205 FTIM2_NOR_TWPH(0xe) | \ 206 FTIM2_NOR_TWP(0x1c)) 207 #define CONFIG_SYS_NOR_FTIM3 0 208 209 #define CONFIG_FLASH_CFI_DRIVER 210 #define CONFIG_SYS_FLASH_CFI 211 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 212 #define CONFIG_SYS_FLASH_QUIET_TEST 213 #define CONFIG_FLASH_SHOW_PROGRESS 45 214 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 215 #define CONFIG_SYS_WRITE_SWAPPED_DATA 216 217 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 218 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 221 222 #define CONFIG_SYS_FLASH_EMPTY_INFO 223 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 224 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 225 226 /* 227 * NAND Flash Definitions 228 */ 229 #define CONFIG_NAND_FSL_IFC 230 231 #define CONFIG_SYS_NAND_BASE 0x7e800000 232 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 233 234 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 235 236 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 237 | CSPR_PORT_SIZE_8 \ 238 | CSPR_MSEL_NAND \ 239 | CSPR_V) 240 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 241 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 242 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 243 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 244 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 245 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 246 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 247 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 248 249 #define CONFIG_SYS_NAND_ONFI_DETECTION 250 251 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 252 FTIM0_NAND_TWP(0x18) | \ 253 FTIM0_NAND_TWCHT(0x7) | \ 254 FTIM0_NAND_TWH(0xa)) 255 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 256 FTIM1_NAND_TWBE(0x39) | \ 257 FTIM1_NAND_TRR(0xe) | \ 258 FTIM1_NAND_TRP(0x18)) 259 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 260 FTIM2_NAND_TREH(0xa) | \ 261 FTIM2_NAND_TWHRE(0x1e)) 262 #define CONFIG_SYS_NAND_FTIM3 0x0 263 264 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 265 #define CONFIG_SYS_MAX_NAND_DEVICE 1 266 #define CONFIG_CMD_NAND 267 268 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 269 #endif 270 271 /* 272 * QIXIS Definitions 273 */ 274 #define CONFIG_FSL_QIXIS 275 276 #ifdef CONFIG_FSL_QIXIS 277 #define QIXIS_BASE 0x7fb00000 278 #define QIXIS_BASE_PHYS QIXIS_BASE 279 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 280 #define QIXIS_LBMAP_SWITCH 6 281 #define QIXIS_LBMAP_MASK 0x0f 282 #define QIXIS_LBMAP_SHIFT 0 283 #define QIXIS_LBMAP_DFLTBANK 0x00 284 #define QIXIS_LBMAP_ALTBANK 0x04 285 #define QIXIS_PWR_CTL 0x21 286 #define QIXIS_PWR_CTL_POWEROFF 0x80 287 #define QIXIS_RST_CTL_RESET 0x44 288 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 289 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 290 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 291 #define QIXIS_CTL_SYS 0x5 292 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 293 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 294 #define QIXIS_RST_FORCE_3 0x45 295 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 296 #define QIXIS_PWR_CTL2 0x21 297 #define QIXIS_PWR_CTL2_PCTL 0x2 298 299 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 300 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 301 CSPR_PORT_SIZE_8 | \ 302 CSPR_MSEL_GPCM | \ 303 CSPR_V) 304 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 305 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 306 CSOR_NOR_NOR_MODE_AVD_NOR | \ 307 CSOR_NOR_TRHZ_80) 308 309 /* 310 * QIXIS Timing parameters for IFC GPCM 311 */ 312 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 313 FTIM0_GPCM_TEADC(0xe) | \ 314 FTIM0_GPCM_TEAHC(0xe)) 315 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 316 FTIM1_GPCM_TRAD(0x1f)) 317 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 318 FTIM2_GPCM_TCH(0xe) | \ 319 FTIM2_GPCM_TWP(0xf0)) 320 #define CONFIG_SYS_FPGA_FTIM3 0x0 321 #endif 322 323 #if defined(CONFIG_NAND_BOOT) 324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 349 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 350 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 351 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 352 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 353 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 354 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 355 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 356 #else 357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 366 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 367 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 368 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 369 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 370 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 371 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 372 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 373 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 374 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 375 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 376 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 377 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 378 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 379 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 380 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 381 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 382 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 383 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 384 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 385 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 386 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 387 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 388 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 389 #endif 390 391 /* 392 * Serial Port 393 */ 394 #ifdef CONFIG_LPUART 395 #define CONFIG_LPUART_32B_REG 396 #else 397 #define CONFIG_CONS_INDEX 1 398 #define CONFIG_SYS_NS16550_SERIAL 399 #ifndef CONFIG_DM_SERIAL 400 #define CONFIG_SYS_NS16550_REG_SIZE 1 401 #endif 402 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 403 #endif 404 405 #define CONFIG_BAUDRATE 115200 406 407 /* 408 * I2C 409 */ 410 #define CONFIG_SYS_I2C 411 #define CONFIG_SYS_I2C_MXC 412 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 413 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 414 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 415 416 /* 417 * I2C bus multiplexer 418 */ 419 #define I2C_MUX_PCA_ADDR_PRI 0x77 420 #define I2C_MUX_CH_DEFAULT 0x8 421 #define I2C_MUX_CH_CH7301 0xC 422 423 /* 424 * MMC 425 */ 426 #define CONFIG_MMC 427 #define CONFIG_FSL_ESDHC 428 #define CONFIG_GENERIC_MMC 429 430 #define CONFIG_DOS_PARTITION 431 432 /* SPI */ 433 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 434 /* QSPI */ 435 #define QSPI0_AMBA_BASE 0x40000000 436 #define FSL_QSPI_FLASH_SIZE (1 << 24) 437 #define FSL_QSPI_FLASH_NUM 2 438 439 /* DSPI */ 440 441 /* DM SPI */ 442 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 443 #define CONFIG_DM_SPI_FLASH 444 #define CONFIG_SPI_FLASH_DATAFLASH 445 #endif 446 #endif 447 448 /* 449 * USB 450 */ 451 /* EHCI Support - disbaled by default */ 452 /*#define CONFIG_HAS_FSL_DR_USB*/ 453 454 #ifdef CONFIG_HAS_FSL_DR_USB 455 #define CONFIG_USB_EHCI 456 #define CONFIG_USB_EHCI_FSL 457 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 458 #endif 459 460 /*XHCI Support - enabled by default*/ 461 #define CONFIG_HAS_FSL_XHCI_USB 462 463 #ifdef CONFIG_HAS_FSL_XHCI_USB 464 #define CONFIG_USB_XHCI_FSL 465 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 466 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 467 #endif 468 469 /* 470 * Video 471 */ 472 #define CONFIG_FSL_DCU_FB 473 474 #ifdef CONFIG_FSL_DCU_FB 475 #define CONFIG_VIDEO 476 #define CONFIG_CMD_BMP 477 #define CONFIG_CFB_CONSOLE 478 #define CONFIG_VGA_AS_SINGLE_DEVICE 479 #define CONFIG_VIDEO_LOGO 480 #define CONFIG_VIDEO_BMP_LOGO 481 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 482 483 #define CONFIG_FSL_DIU_CH7301 484 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 485 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 486 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 487 #endif 488 489 /* 490 * eTSEC 491 */ 492 #define CONFIG_TSEC_ENET 493 494 #ifdef CONFIG_TSEC_ENET 495 #define CONFIG_MII 496 #define CONFIG_MII_DEFAULT_TSEC 3 497 #define CONFIG_TSEC1 1 498 #define CONFIG_TSEC1_NAME "eTSEC1" 499 #define CONFIG_TSEC2 1 500 #define CONFIG_TSEC2_NAME "eTSEC2" 501 #define CONFIG_TSEC3 1 502 #define CONFIG_TSEC3_NAME "eTSEC3" 503 504 #define TSEC1_PHY_ADDR 1 505 #define TSEC2_PHY_ADDR 2 506 #define TSEC3_PHY_ADDR 3 507 508 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 509 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 510 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 511 512 #define TSEC1_PHYIDX 0 513 #define TSEC2_PHYIDX 0 514 #define TSEC3_PHYIDX 0 515 516 #define CONFIG_ETHPRIME "eTSEC1" 517 518 #define CONFIG_PHY_GIGE 519 #define CONFIG_PHYLIB 520 #define CONFIG_PHY_REALTEK 521 522 #define CONFIG_HAS_ETH0 523 #define CONFIG_HAS_ETH1 524 #define CONFIG_HAS_ETH2 525 526 #define CONFIG_FSL_SGMII_RISER 1 527 #define SGMII_RISER_PHY_OFFSET 0x1b 528 529 #ifdef CONFIG_FSL_SGMII_RISER 530 #define CONFIG_SYS_TBIPA_VALUE 8 531 #endif 532 533 #endif 534 535 /* PCIe */ 536 #define CONFIG_PCI /* Enable PCI/PCIE */ 537 #define CONFIG_PCIE1 /* PCIE controller 1 */ 538 #define CONFIG_PCIE2 /* PCIE controller 2 */ 539 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 540 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 541 542 #define CONFIG_SYS_PCI_64BIT 543 544 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 545 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 546 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 547 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 548 549 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 550 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 551 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 552 553 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 554 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 555 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 556 557 #ifdef CONFIG_PCI 558 #define CONFIG_PCI_PNP 559 #define CONFIG_PCI_SCAN_SHOW 560 #define CONFIG_CMD_PCI 561 #endif 562 563 #define CONFIG_CMDLINE_TAG 564 #define CONFIG_CMDLINE_EDITING 565 566 #define CONFIG_ARMV7_NONSEC 567 #define CONFIG_ARMV7_VIRT 568 #define CONFIG_PEN_ADDR_BIG_ENDIAN 569 #define CONFIG_LAYERSCAPE_NS_ACCESS 570 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 571 #define CONFIG_TIMER_CLK_FREQ 12500000 572 573 #define CONFIG_HWCONFIG 574 #define HWCONFIG_BUFFER_SIZE 256 575 576 #define CONFIG_FSL_DEVICE_DISABLE 577 578 579 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 580 581 #ifdef CONFIG_LPUART 582 #define CONFIG_EXTRA_ENV_SETTINGS \ 583 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 584 "fdt_high=0xffffffff\0" \ 585 "initrd_high=0xffffffff\0" \ 586 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 587 #else 588 #define CONFIG_EXTRA_ENV_SETTINGS \ 589 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 590 "fdt_high=0xffffffff\0" \ 591 "initrd_high=0xffffffff\0" \ 592 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 593 #endif 594 595 /* 596 * Miscellaneous configurable options 597 */ 598 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 599 #define CONFIG_AUTO_COMPLETE 600 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 601 #define CONFIG_SYS_PBSIZE \ 602 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 603 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 604 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 605 606 #define CONFIG_SYS_MEMTEST_START 0x80000000 607 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 608 609 #define CONFIG_SYS_LOAD_ADDR 0x82000000 610 611 #define CONFIG_LS102XA_STREAM_ID 612 613 /* 614 * Stack sizes 615 * The stack sizes are set up in start.S using the settings below 616 */ 617 #define CONFIG_STACKSIZE (30 * 1024) 618 619 #define CONFIG_SYS_INIT_SP_OFFSET \ 620 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 621 #define CONFIG_SYS_INIT_SP_ADDR \ 622 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 623 624 #ifdef CONFIG_SPL_BUILD 625 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 626 #else 627 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 628 #endif 629 630 /* 631 * Environment 632 */ 633 #define CONFIG_ENV_OVERWRITE 634 635 #if defined(CONFIG_SD_BOOT) 636 #define CONFIG_ENV_OFFSET 0x100000 637 #define CONFIG_ENV_IS_IN_MMC 638 #define CONFIG_SYS_MMC_ENV_DEV 0 639 #define CONFIG_ENV_SIZE 0x2000 640 #elif defined(CONFIG_QSPI_BOOT) 641 #define CONFIG_ENV_IS_IN_SPI_FLASH 642 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 643 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 644 #define CONFIG_ENV_SECT_SIZE 0x10000 645 #elif defined(CONFIG_NAND_BOOT) 646 #define CONFIG_ENV_IS_IN_NAND 647 #define CONFIG_ENV_SIZE 0x2000 648 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 649 #else 650 #define CONFIG_ENV_IS_IN_FLASH 651 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 652 #define CONFIG_ENV_SIZE 0x2000 653 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 654 #endif 655 656 #define CONFIG_MISC_INIT_R 657 658 /* Hash command with SHA acceleration supported in hardware */ 659 #ifdef CONFIG_FSL_CAAM 660 #define CONFIG_CMD_HASH 661 #define CONFIG_SHA_HW_ACCEL 662 #endif 663 664 #include <asm/fsl_secure_boot.h> 665 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 666 667 #endif 668