1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_BOARD_EARLY_INIT_F 22 23 #define CONFIG_DEEP_SLEEP 24 #if defined(CONFIG_DEEP_SLEEP) 25 #define CONFIG_SILENT_CONSOLE 26 #endif 27 28 /* 29 * Size of malloc() pool 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 32 33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 35 36 /* 37 * Generic Timer Definitions 38 */ 39 #define GENERIC_TIMER_CLK 12500000 40 41 #ifndef __ASSEMBLY__ 42 unsigned long get_board_sys_clk(void); 43 unsigned long get_board_ddr_clk(void); 44 #endif 45 46 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 47 #define CONFIG_SYS_CLK_FREQ 100000000 48 #define CONFIG_DDR_CLK_FREQ 100000000 49 #define CONFIG_QIXIS_I2C_ACCESS 50 #else 51 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 52 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 53 #endif 54 55 #ifdef CONFIG_RAMBOOT_PBL 56 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 57 #endif 58 59 #ifdef CONFIG_SD_BOOT 60 #ifdef CONFIG_SD_BOOT_QSPI 61 #define CONFIG_SYS_FSL_PBL_RCW \ 62 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 63 #else 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 66 #endif 67 #define CONFIG_SPL_FRAMEWORK 68 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 71 72 #define CONFIG_SPL_TEXT_BASE 0x10000000 73 #define CONFIG_SPL_MAX_SIZE 0x1a000 74 #define CONFIG_SPL_STACK 0x1001d000 75 #define CONFIG_SPL_PAD_TO 0x1c000 76 #define CONFIG_SYS_TEXT_BASE 0x82000000 77 78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 79 CONFIG_SYS_MONITOR_LEN) 80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 83 #define CONFIG_SYS_MONITOR_LEN 0xc0000 84 #endif 85 86 #ifdef CONFIG_QSPI_BOOT 87 #define CONFIG_SYS_TEXT_BASE 0x40010000 88 #endif 89 90 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 91 #define CONFIG_SYS_NO_FLASH 92 #endif 93 94 #ifdef CONFIG_NAND_BOOT 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 96 #define CONFIG_SPL_FRAMEWORK 97 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 98 99 #define CONFIG_SPL_TEXT_BASE 0x10000000 100 #define CONFIG_SPL_MAX_SIZE 0x1a000 101 #define CONFIG_SPL_STACK 0x1001d000 102 #define CONFIG_SPL_PAD_TO 0x1c000 103 #define CONFIG_SYS_TEXT_BASE 0x82000000 104 105 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 107 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 108 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 109 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 110 111 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 112 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 113 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 114 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 115 #define CONFIG_SYS_MONITOR_LEN 0x80000 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0x60100000 120 #endif 121 122 #define CONFIG_NR_DRAM_BANKS 1 123 124 #define CONFIG_DDR_SPD 125 #define SPD_EEPROM_ADDRESS 0x51 126 #define CONFIG_SYS_SPD_BUS_NUM 0 127 128 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 129 #ifndef CONFIG_SYS_FSL_DDR4 130 #define CONFIG_SYS_DDR_RAW_TIMING 131 #endif 132 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 133 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 134 135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 137 138 #define CONFIG_DDR_ECC 139 #ifdef CONFIG_DDR_ECC 140 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 141 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 142 #endif 143 144 #define CONFIG_FSL_CAAM /* Enable CAAM */ 145 146 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 147 !defined(CONFIG_QSPI_BOOT) 148 #define CONFIG_U_QE 149 #endif 150 151 /* 152 * IFC Definitions 153 */ 154 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 155 #define CONFIG_FSL_IFC 156 #define CONFIG_SYS_FLASH_BASE 0x60000000 157 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 158 159 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 160 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 161 CSPR_PORT_SIZE_16 | \ 162 CSPR_MSEL_NOR | \ 163 CSPR_V) 164 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 165 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 166 + 0x8000000) | \ 167 CSPR_PORT_SIZE_16 | \ 168 CSPR_MSEL_NOR | \ 169 CSPR_V) 170 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 171 172 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 173 CSOR_NOR_TRHZ_80) 174 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TEAHC(0x5)) 177 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 FTIM1_NOR_TRAD_NOR(0x1a) | \ 179 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TWPH(0xe) | \ 183 FTIM2_NOR_TWP(0x1c)) 184 #define CONFIG_SYS_NOR_FTIM3 0 185 186 #define CONFIG_FLASH_CFI_DRIVER 187 #define CONFIG_SYS_FLASH_CFI 188 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189 #define CONFIG_SYS_FLASH_QUIET_TEST 190 #define CONFIG_FLASH_SHOW_PROGRESS 45 191 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 192 #define CONFIG_SYS_WRITE_SWAPPED_DATA 193 194 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 195 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 199 #define CONFIG_SYS_FLASH_EMPTY_INFO 200 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 201 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 202 203 /* 204 * NAND Flash Definitions 205 */ 206 #define CONFIG_NAND_FSL_IFC 207 208 #define CONFIG_SYS_NAND_BASE 0x7e800000 209 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 210 211 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 212 213 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 214 | CSPR_PORT_SIZE_8 \ 215 | CSPR_MSEL_NAND \ 216 | CSPR_V) 217 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 218 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 219 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 220 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 221 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 222 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 223 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 224 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 225 226 #define CONFIG_SYS_NAND_ONFI_DETECTION 227 228 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 229 FTIM0_NAND_TWP(0x18) | \ 230 FTIM0_NAND_TWCHT(0x7) | \ 231 FTIM0_NAND_TWH(0xa)) 232 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 233 FTIM1_NAND_TWBE(0x39) | \ 234 FTIM1_NAND_TRR(0xe) | \ 235 FTIM1_NAND_TRP(0x18)) 236 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 237 FTIM2_NAND_TREH(0xa) | \ 238 FTIM2_NAND_TWHRE(0x1e)) 239 #define CONFIG_SYS_NAND_FTIM3 0x0 240 241 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 242 #define CONFIG_SYS_MAX_NAND_DEVICE 1 243 #define CONFIG_CMD_NAND 244 245 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 246 #endif 247 248 /* 249 * QIXIS Definitions 250 */ 251 #define CONFIG_FSL_QIXIS 252 253 #ifdef CONFIG_FSL_QIXIS 254 #define QIXIS_BASE 0x7fb00000 255 #define QIXIS_BASE_PHYS QIXIS_BASE 256 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 257 #define QIXIS_LBMAP_SWITCH 6 258 #define QIXIS_LBMAP_MASK 0x0f 259 #define QIXIS_LBMAP_SHIFT 0 260 #define QIXIS_LBMAP_DFLTBANK 0x00 261 #define QIXIS_LBMAP_ALTBANK 0x04 262 #define QIXIS_PWR_CTL 0x21 263 #define QIXIS_PWR_CTL_POWEROFF 0x80 264 #define QIXIS_RST_CTL_RESET 0x44 265 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 266 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 267 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 268 #define QIXIS_CTL_SYS 0x5 269 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 270 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 271 #define QIXIS_RST_FORCE_3 0x45 272 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 273 #define QIXIS_PWR_CTL2 0x21 274 #define QIXIS_PWR_CTL2_PCTL 0x2 275 276 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 277 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 278 CSPR_PORT_SIZE_8 | \ 279 CSPR_MSEL_GPCM | \ 280 CSPR_V) 281 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 282 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 283 CSOR_NOR_NOR_MODE_AVD_NOR | \ 284 CSOR_NOR_TRHZ_80) 285 286 /* 287 * QIXIS Timing parameters for IFC GPCM 288 */ 289 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 290 FTIM0_GPCM_TEADC(0xe) | \ 291 FTIM0_GPCM_TEAHC(0xe)) 292 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 293 FTIM1_GPCM_TRAD(0x1f)) 294 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 295 FTIM2_GPCM_TCH(0xe) | \ 296 FTIM2_GPCM_TWP(0xf0)) 297 #define CONFIG_SYS_FPGA_FTIM3 0x0 298 #endif 299 300 #if defined(CONFIG_NAND_BOOT) 301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 309 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 310 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 311 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 318 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 319 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 326 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 327 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 328 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 329 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 330 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 331 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 332 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 333 #else 334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 359 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 360 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 361 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 362 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 363 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 364 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 365 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 366 #endif 367 368 /* 369 * Serial Port 370 */ 371 #ifdef CONFIG_LPUART 372 #define CONFIG_LPUART_32B_REG 373 #else 374 #define CONFIG_CONS_INDEX 1 375 #define CONFIG_SYS_NS16550_SERIAL 376 #ifndef CONFIG_DM_SERIAL 377 #define CONFIG_SYS_NS16550_REG_SIZE 1 378 #endif 379 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 380 #endif 381 382 #define CONFIG_BAUDRATE 115200 383 384 /* 385 * I2C 386 */ 387 #define CONFIG_SYS_I2C 388 #define CONFIG_SYS_I2C_MXC 389 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 390 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 391 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 392 393 /* 394 * I2C bus multiplexer 395 */ 396 #define I2C_MUX_PCA_ADDR_PRI 0x77 397 #define I2C_MUX_CH_DEFAULT 0x8 398 #define I2C_MUX_CH_CH7301 0xC 399 400 /* 401 * MMC 402 */ 403 #define CONFIG_MMC 404 #define CONFIG_FSL_ESDHC 405 #define CONFIG_GENERIC_MMC 406 407 #define CONFIG_DOS_PARTITION 408 409 /* SPI */ 410 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 411 /* QSPI */ 412 #define QSPI0_AMBA_BASE 0x40000000 413 #define FSL_QSPI_FLASH_SIZE (1 << 24) 414 #define FSL_QSPI_FLASH_NUM 2 415 416 /* DSPI */ 417 418 /* DM SPI */ 419 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 420 #define CONFIG_DM_SPI_FLASH 421 #define CONFIG_SPI_FLASH_DATAFLASH 422 #endif 423 #endif 424 425 /* 426 * USB 427 */ 428 /* EHCI Support - disbaled by default */ 429 /*#define CONFIG_HAS_FSL_DR_USB*/ 430 431 #ifdef CONFIG_HAS_FSL_DR_USB 432 #define CONFIG_USB_EHCI 433 #define CONFIG_USB_EHCI_FSL 434 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 435 #endif 436 437 /*XHCI Support - enabled by default*/ 438 #define CONFIG_HAS_FSL_XHCI_USB 439 440 #ifdef CONFIG_HAS_FSL_XHCI_USB 441 #define CONFIG_USB_XHCI_FSL 442 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 443 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 444 #endif 445 446 /* 447 * Video 448 */ 449 #define CONFIG_FSL_DCU_FB 450 451 #ifdef CONFIG_FSL_DCU_FB 452 #define CONFIG_VIDEO 453 #define CONFIG_CMD_BMP 454 #define CONFIG_CFB_CONSOLE 455 #define CONFIG_VGA_AS_SINGLE_DEVICE 456 #define CONFIG_VIDEO_LOGO 457 #define CONFIG_VIDEO_BMP_LOGO 458 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 459 460 #define CONFIG_FSL_DIU_CH7301 461 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 462 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 463 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 464 #endif 465 466 /* 467 * eTSEC 468 */ 469 #define CONFIG_TSEC_ENET 470 471 #ifdef CONFIG_TSEC_ENET 472 #define CONFIG_MII 473 #define CONFIG_MII_DEFAULT_TSEC 3 474 #define CONFIG_TSEC1 1 475 #define CONFIG_TSEC1_NAME "eTSEC1" 476 #define CONFIG_TSEC2 1 477 #define CONFIG_TSEC2_NAME "eTSEC2" 478 #define CONFIG_TSEC3 1 479 #define CONFIG_TSEC3_NAME "eTSEC3" 480 481 #define TSEC1_PHY_ADDR 1 482 #define TSEC2_PHY_ADDR 2 483 #define TSEC3_PHY_ADDR 3 484 485 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 486 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 487 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 488 489 #define TSEC1_PHYIDX 0 490 #define TSEC2_PHYIDX 0 491 #define TSEC3_PHYIDX 0 492 493 #define CONFIG_ETHPRIME "eTSEC1" 494 495 #define CONFIG_PHY_GIGE 496 #define CONFIG_PHYLIB 497 #define CONFIG_PHY_REALTEK 498 499 #define CONFIG_HAS_ETH0 500 #define CONFIG_HAS_ETH1 501 #define CONFIG_HAS_ETH2 502 503 #define CONFIG_FSL_SGMII_RISER 1 504 #define SGMII_RISER_PHY_OFFSET 0x1b 505 506 #ifdef CONFIG_FSL_SGMII_RISER 507 #define CONFIG_SYS_TBIPA_VALUE 8 508 #endif 509 510 #endif 511 512 /* PCIe */ 513 #define CONFIG_PCI /* Enable PCI/PCIE */ 514 #define CONFIG_PCIE1 /* PCIE controller 1 */ 515 #define CONFIG_PCIE2 /* PCIE controller 2 */ 516 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 517 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 518 519 #define CONFIG_SYS_PCI_64BIT 520 521 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 522 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 523 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 524 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 525 526 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 527 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 528 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 529 530 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 531 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 532 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 533 534 #ifdef CONFIG_PCI 535 #define CONFIG_PCI_PNP 536 #define CONFIG_PCI_SCAN_SHOW 537 #define CONFIG_CMD_PCI 538 #endif 539 540 #define CONFIG_CMDLINE_TAG 541 #define CONFIG_CMDLINE_EDITING 542 543 #define CONFIG_PEN_ADDR_BIG_ENDIAN 544 #define CONFIG_LAYERSCAPE_NS_ACCESS 545 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 546 #define CONFIG_TIMER_CLK_FREQ 12500000 547 548 #define CONFIG_HWCONFIG 549 #define HWCONFIG_BUFFER_SIZE 256 550 551 #define CONFIG_FSL_DEVICE_DISABLE 552 553 554 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 555 556 #ifdef CONFIG_LPUART 557 #define CONFIG_EXTRA_ENV_SETTINGS \ 558 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 559 "fdt_high=0xffffffff\0" \ 560 "initrd_high=0xffffffff\0" \ 561 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 562 #else 563 #define CONFIG_EXTRA_ENV_SETTINGS \ 564 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 565 "fdt_high=0xffffffff\0" \ 566 "initrd_high=0xffffffff\0" \ 567 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 568 #endif 569 570 /* 571 * Miscellaneous configurable options 572 */ 573 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 574 #define CONFIG_AUTO_COMPLETE 575 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 576 #define CONFIG_SYS_PBSIZE \ 577 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 578 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 579 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 580 581 #define CONFIG_SYS_MEMTEST_START 0x80000000 582 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 583 584 #define CONFIG_SYS_LOAD_ADDR 0x82000000 585 586 #define CONFIG_LS102XA_STREAM_ID 587 588 /* 589 * Stack sizes 590 * The stack sizes are set up in start.S using the settings below 591 */ 592 #define CONFIG_STACKSIZE (30 * 1024) 593 594 #define CONFIG_SYS_INIT_SP_OFFSET \ 595 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 596 #define CONFIG_SYS_INIT_SP_ADDR \ 597 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 598 599 #ifdef CONFIG_SPL_BUILD 600 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 601 #else 602 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 603 #endif 604 605 /* 606 * Environment 607 */ 608 #define CONFIG_ENV_OVERWRITE 609 610 #if defined(CONFIG_SD_BOOT) 611 #define CONFIG_ENV_OFFSET 0x100000 612 #define CONFIG_ENV_IS_IN_MMC 613 #define CONFIG_SYS_MMC_ENV_DEV 0 614 #define CONFIG_ENV_SIZE 0x2000 615 #elif defined(CONFIG_QSPI_BOOT) 616 #define CONFIG_ENV_IS_IN_SPI_FLASH 617 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 618 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 619 #define CONFIG_ENV_SECT_SIZE 0x10000 620 #elif defined(CONFIG_NAND_BOOT) 621 #define CONFIG_ENV_IS_IN_NAND 622 #define CONFIG_ENV_SIZE 0x2000 623 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 624 #else 625 #define CONFIG_ENV_IS_IN_FLASH 626 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 627 #define CONFIG_ENV_SIZE 0x2000 628 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 629 #endif 630 631 #define CONFIG_MISC_INIT_R 632 633 /* Hash command with SHA acceleration supported in hardware */ 634 #ifdef CONFIG_FSL_CAAM 635 #define CONFIG_CMD_HASH 636 #define CONFIG_SHA_HW_ACCEL 637 #endif 638 639 #include <asm/fsl_secure_boot.h> 640 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 641 642 #endif 643