1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_BOARD_EARLY_INIT_F 17 18 /* 19 * Size of malloc() pool 20 */ 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 22 23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 25 26 /* XHCI Support - enabled by default */ 27 #define CONFIG_HAS_FSL_XHCI_USB 28 29 #ifdef CONFIG_HAS_FSL_XHCI_USB 30 #define CONFIG_USB_XHCI_FSL 31 #define CONFIG_USB_XHCI_DWC3 32 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 33 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 34 #endif 35 36 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 37 #define CONFIG_USB_STORAGE 38 #define CONFIG_CMD_EXT2 39 #endif 40 41 /* 42 * Generic Timer Definitions 43 */ 44 #define GENERIC_TIMER_CLK 12500000 45 46 #define CONFIG_SYS_CLK_FREQ 100000000 47 #define CONFIG_DDR_CLK_FREQ 100000000 48 49 /* 50 * DDR: 800 MHz ( 1600 MT/s data rate ) 51 */ 52 53 #define DDR_SDRAM_CFG 0x470c0008 54 #define DDR_CS0_BNDS 0x008000bf 55 #define DDR_CS0_CONFIG 0x80014302 56 #define DDR_TIMING_CFG_0 0x50550004 57 #define DDR_TIMING_CFG_1 0xbcb38c56 58 #define DDR_TIMING_CFG_2 0x0040d120 59 #define DDR_TIMING_CFG_3 0x010e1000 60 #define DDR_TIMING_CFG_4 0x00000001 61 #define DDR_TIMING_CFG_5 0x03401400 62 #define DDR_SDRAM_CFG_2 0x00401010 63 #define DDR_SDRAM_MODE 0x00061c60 64 #define DDR_SDRAM_MODE_2 0x00180000 65 #define DDR_SDRAM_INTERVAL 0x18600618 66 #define DDR_DDR_WRLVL_CNTL 0x8655f605 67 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 68 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 69 #define DDR_DDR_CDR1 0x80040000 70 #define DDR_DDR_CDR2 0x00000001 71 #define DDR_SDRAM_CLK_CNTL 0x02000000 72 #define DDR_DDR_ZQ_CNTL 0x89080600 73 #define DDR_CS0_CONFIG_2 0 74 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 75 #define SDRAM_CFG2_D_INIT 0x00000010 76 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 77 #define SDRAM_CFG2_FRC_SR 0x80000000 78 #define SDRAM_CFG_BI 0x00000001 79 80 #ifdef CONFIG_RAMBOOT_PBL 81 #define CONFIG_SYS_FSL_PBL_PBI \ 82 board/freescale/ls1021aiot/ls102xa_pbi.cfg 83 #endif 84 85 #ifdef CONFIG_SD_BOOT 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 88 #define CONFIG_SPL_FRAMEWORK 89 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 90 #define CONFIG_SPL_LIBCOMMON_SUPPORT 91 #define CONFIG_SPL_LIBGENERIC_SUPPORT 92 #define CONFIG_SPL_ENV_SUPPORT 93 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 94 #define CONFIG_SPL_I2C_SUPPORT 95 #define CONFIG_SPL_WATCHDOG_SUPPORT 96 #define CONFIG_SPL_SERIAL_SUPPORT 97 #define CONFIG_SPL_MMC_SUPPORT 98 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 99 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 100 101 #define CONFIG_SPL_TEXT_BASE 0x10000000 102 #define CONFIG_SPL_MAX_SIZE 0x1a000 103 #define CONFIG_SPL_STACK 0x1001d000 104 #define CONFIG_SPL_PAD_TO 0x1c000 105 #define CONFIG_SYS_TEXT_BASE 0x82000000 106 107 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 108 CONFIG_SYS_MONITOR_LEN) 109 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 110 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 111 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 112 #define CONFIG_SYS_MONITOR_LEN 0x80000 113 #define CONFIG_SYS_NO_FLASH 114 #endif 115 116 #ifdef CONFIG_QSPI_BOOT 117 #define CONFIG_SYS_TEXT_BASE 0x40010000 118 #endif 119 120 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 121 #define CONFIG_SYS_NO_FLASH 122 #endif 123 124 #define CONFIG_NR_DRAM_BANKS 1 125 126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 128 129 #define CONFIG_FSL_CAAM /* Enable CAAM */ 130 131 /* 132 * Serial Port 133 */ 134 #define CONFIG_CONS_INDEX 1 135 #define CONFIG_SYS_NS16550_SERIAL 136 #define CONFIG_SYS_NS16550_REG_SIZE 1 137 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 138 #define CONFIG_BAUDRATE 115200 139 140 /* 141 * I2C 142 */ 143 #define CONFIG_CMD_I2C 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_I2C_MXC 146 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 147 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 148 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 156 157 /* 158 * MMC 159 */ 160 #define CONFIG_MMC 161 #define CONFIG_CMD_MMC 162 #define CONFIG_FSL_ESDHC 163 #define CONFIG_GENERIC_MMC 164 165 /* SATA */ 166 #define CONFIG_BOARD_LATE_INIT 167 #define CONFIG_CMD_SCSI 168 #define CONFIG_LIBATA 169 #define CONFIG_SCSI_AHCI 170 #define CONFIG_SCSI_AHCI_PLAT 171 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 172 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 173 #endif 174 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 175 PCI_DEVICE_ID_FREESCALE_AHCI} 176 177 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 178 #define CONFIG_SYS_SCSI_MAX_LUN 1 179 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 180 CONFIG_SYS_SCSI_MAX_LUN) 181 182 #define CONFIG_CMD_FAT 183 #define CONFIG_DOS_PARTITION 184 185 /* SPI */ 186 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 187 #define CONFIG_SPI_FLASH_SPANSION 188 189 /* QSPI */ 190 #define QSPI0_AMBA_BASE 0x40000000 191 #define FSL_QSPI_FLASH_SIZE (1 << 24) 192 #define FSL_QSPI_FLASH_NUM 2 193 #define CONFIG_SPI_FLASH_BAR 194 #define CONFIG_SPI_FLASH_SPANSION 195 #endif 196 197 /* DM SPI */ 198 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 199 #define CONFIG_CMD_SF 200 #define CONFIG_DM_SPI_FLASH 201 #endif 202 203 /* 204 * eTSEC 205 */ 206 #define CONFIG_TSEC_ENET 207 208 #ifdef CONFIG_TSEC_ENET 209 #define CONFIG_MII 210 #define CONFIG_MII_DEFAULT_TSEC 1 211 #define CONFIG_TSEC1 1 212 #define CONFIG_TSEC1_NAME "eTSEC1" 213 #define CONFIG_TSEC2 1 214 #define CONFIG_TSEC2_NAME "eTSEC2" 215 216 #define TSEC1_PHY_ADDR 1 217 #define TSEC2_PHY_ADDR 3 218 219 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 220 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 221 222 #define TSEC1_PHYIDX 0 223 #define TSEC2_PHYIDX 0 224 225 #define CONFIG_ETHPRIME "eTSEC2" 226 227 #define CONFIG_PHY_GIGE 228 #define CONFIG_PHYLIB 229 #define CONFIG_PHY_ATHEROS 230 231 #define CONFIG_HAS_ETH0 232 #define CONFIG_HAS_ETH1 233 #define CONFIG_HAS_ETH2 234 #endif 235 236 /* PCIe */ 237 #define CONFIG_PCI /* Enable PCI/PCIE */ 238 #define CONFIG_PCIE1 /* PCIE controler 1 */ 239 #define CONFIG_PCIE2 /* PCIE controler 2 */ 240 241 /* Use common FSL Layerscape PCIe code */ 242 #define CONFIG_PCIE_LAYERSCAPE 243 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 244 245 #define CONFIG_SYS_PCI_64BIT 246 247 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 248 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 249 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 250 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 251 252 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 254 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 255 256 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 257 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 258 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 259 260 #ifdef CONFIG_PCI 261 #define CONFIG_PCI_PNP 262 #define CONFIG_PCI_SCAN_SHOW 263 #define CONFIG_CMD_PCI 264 #endif 265 266 #define CONFIG_CMD_PING 267 #define CONFIG_CMD_DHCP 268 #define CONFIG_CMD_MII 269 270 #define CONFIG_CMDLINE_TAG 271 #define CONFIG_CMDLINE_EDITING 272 273 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) 274 #undef CONFIG_CMD_IMLS 275 #endif 276 277 #define CONFIG_PEN_ADDR_BIG_ENDIAN 278 #define CONFIG_LAYERSCAPE_NS_ACCESS 279 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 280 #define CONFIG_TIMER_CLK_FREQ 12500000 281 282 #define CONFIG_HWCONFIG 283 #define HWCONFIG_BUFFER_SIZE 256 284 285 #define CONFIG_FSL_DEVICE_DISABLE 286 287 #define CONFIG_EXTRA_ENV_SETTINGS \ 288 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 289 "initrd_high=0xffffffff\0" \ 290 "fdt_high=0xffffffff\0" 291 292 /* 293 * Miscellaneous configurable options 294 */ 295 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 297 #define CONFIG_AUTO_COMPLETE 298 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 299 #define CONFIG_SYS_PBSIZE \ 300 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 301 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 302 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 303 304 #define CONFIG_CMD_GREPENV 305 #define CONFIG_CMD_MEMINFO 306 307 #define CONFIG_SYS_LOAD_ADDR 0x82000000 308 309 #define CONFIG_LS102XA_STREAM_ID 310 311 /* 312 * Stack sizes 313 * The stack sizes are set up in start.S using the settings below 314 */ 315 #define CONFIG_STACKSIZE (30 * 1024) 316 317 #define CONFIG_SYS_INIT_SP_OFFSET \ 318 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 319 #define CONFIG_SYS_INIT_SP_ADDR \ 320 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 321 322 #ifdef CONFIG_SPL_BUILD 323 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 324 #else 325 /* start of monitor */ 326 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 327 #endif 328 329 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 330 331 /* 332 * Environment 333 */ 334 335 #define CONFIG_ENV_OVERWRITE 336 337 #if defined(CONFIG_SD_BOOT) 338 #define CONFIG_ENV_OFFSET 0x100000 339 #define CONFIG_ENV_IS_IN_MMC 340 #define CONFIG_SYS_MMC_ENV_DEV 0 341 #define CONFIG_ENV_SIZE 0x2000 342 #elif defined(CONFIG_QSPI_BOOT) 343 #define CONFIG_ENV_IS_IN_SPI_FLASH 344 #define CONFIG_ENV_SIZE 0x2000 345 #define CONFIG_ENV_OFFSET 0x100000 346 #define CONFIG_ENV_SECT_SIZE 0x10000 347 #endif 348 349 #define CONFIG_OF_BOARD_SETUP 350 #define CONFIG_OF_STDOUT_VIA_ALIAS 351 #define CONFIG_CMD_BOOTZ 352 353 #define CONFIG_MISC_INIT_R 354 355 /* Hash command with SHA acceleration supported in hardware */ 356 357 #ifdef CONFIG_FSL_CAAM 358 359 #define CONFIG_CMD_HASH 360 361 #define CONFIG_SHA_HW_ACCEL 362 363 #endif 364 365 #include <asm/fsl_secure_boot.h> 366 367 #endif 368