1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1012ARDB_H__ 8 #define __LS1012ARDB_H__ 9 10 #include "ls1012a_common.h" 11 12 /* DDR */ 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 15 #define CONFIG_NR_DRAM_BANKS 2 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 17 #define CONFIG_CMD_MEMINFO 18 #define CONFIG_CMD_MEMTEST 19 #define CONFIG_SYS_MEMTEST_START 0x80000000 20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 21 22 /* DDR board-specific timing parameters */ 23 #define CONFIG_MMDC_MDCTL 0x05180000 24 #define CONFIG_MMDC_MDPDC 0x00030035 25 #define CONFIG_MMDC_MDOTC 0x12554000 26 #define CONFIG_MMDC_MDCFG0 0xbabf7954 27 #define CONFIG_MMDC_MDCFG1 0xdb328f64 28 #define CONFIG_MMDC_MDCFG2 0x01ff00db 29 #define CONFIG_MMDC_MDMISC 0x00001680 30 #define CONFIG_MMDC_MDREF 0x0f3c8000 31 #define CONFIG_MMDC_MDRWD 0x00002000 32 #define CONFIG_MMDC_MDOR 0x00bf1023 33 #define CONFIG_MMDC_MDASP 0x0000003f 34 #define CONFIG_MMDC_MPODTCTRL 0x0000022a 35 #define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 36 37 /* 38 * USB 39 */ 40 #define CONFIG_HAS_FSL_XHCI_USB 41 42 #ifdef CONFIG_HAS_FSL_XHCI_USB 43 #define CONFIG_USB_XHCI_FSL 44 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 45 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 46 #endif 47 48 /* 49 * I2C IO expander 50 */ 51 52 #define I2C_MUX_IO1_ADDR 0x24 53 #define __SW_BOOT_MASK 0xFC 54 #define __SW_BOOT_EMU 0x10 55 #define __SW_BOOT_BANK1 0x00 56 #define __SW_BOOT_BANK2 0x01 57 #define __SW_REV_MASK 0x07 58 #define __SW_REV_A 0xF8 59 #define __SW_REV_B 0xF0 60 61 /* MMC */ 62 #define CONFIG_MMC 63 #ifdef CONFIG_MMC 64 #define CONFIG_FSL_ESDHC 65 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 66 #define CONFIG_GENERIC_MMC 67 #define CONFIG_DOS_PARTITION 68 #endif 69 70 /* SATA */ 71 #define CONFIG_LIBATA 72 #define CONFIG_SCSI 73 #define CONFIG_SCSI_AHCI 74 #define CONFIG_SCSI_AHCI_PLAT 75 #define CONFIG_CMD_SCSI 76 #define CONFIG_DOS_PARTITION 77 #define CONFIG_BOARD_LATE_INIT 78 79 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 80 81 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 82 #define CONFIG_SYS_SCSI_MAX_LUN 1 83 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 84 CONFIG_SYS_SCSI_MAX_LUN) 85 #define CONFIG_PCI /* Enable PCI/PCIE */ 86 #define CONFIG_PCIE1 /* PCIE controller 1 */ 87 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 88 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 89 90 #define CONFIG_SYS_PCI_64BIT 91 92 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 93 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 94 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 95 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 96 97 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 98 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 99 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 100 101 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 102 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 103 #define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ 104 105 #define CONFIG_NET_MULTI 106 #define CONFIG_PCI_PNP 107 #define CONFIG_PCI_SCAN_SHOW 108 #define CONFIG_CMD_PCI 109 110 #define CONFIG_CMD_MEMINFO 111 #define CONFIG_CMD_MEMTEST 112 #define CONFIG_SYS_MEMTEST_START 0x80000000 113 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 114 115 #endif /* __LS1012ARDB_H__ */ 116