1 /* 2 * include/configs/lager.h 3 * This file is lager board configuration. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __LAGER_H 11 #define __LAGER_H 12 13 #undef DEBUG 14 #define CONFIG_ARMV7 15 #define CONFIG_R8A7790 16 #define CONFIG_RMOBILE 17 #define CONFIG_RMOBILE_BOARD_STRING "Lager" 18 #define CONFIG_SH_GPIO_PFC 19 #define MACH_TYPE_LAGER 4538 20 #define CONFIG_MACH_TYPE MACH_TYPE_LAGER 21 22 #include <asm/arch/rmobile.h> 23 24 #define CONFIG_CMD_EDITENV 25 #define CONFIG_CMD_SAVEENV 26 #define CONFIG_CMD_MEMORY 27 #define CONFIG_CMD_DFL 28 #define CONFIG_CMD_SDRAM 29 #define CONFIG_CMD_RUN 30 #define CONFIG_CMD_LOADS 31 #define CONFIG_CMD_NET 32 #define CONFIG_CMD_MII 33 #define CONFIG_CMD_PING 34 #define CONFIG_CMD_DHCP 35 #define CONFIG_CMD_NFS 36 #define CONFIG_CMD_BOOTZ 37 38 #define CONFIG_CMD_SF 39 #define CONFIG_CMD_SPI 40 #define CONFIG_SYS_TEXT_BASE 0xE8080000 41 42 #define CONFIG_CMDLINE_TAG 43 #define CONFIG_SETUP_MEMORY_TAGS 44 #define CONFIG_INITRD_TAG 45 #define CONFIG_CMDLINE_EDITING 46 #define CONFIG_OF_LIBFDT 47 48 /* #define CONFIG_OF_LIBFDT */ 49 #define BOARD_LATE_INIT 50 51 #define CONFIG_BAUDRATE 38400 52 #define CONFIG_BOOTDELAY 3 53 #define CONFIG_BOOTARGS "" 54 55 #define CONFIG_VERSION_VARIABLE 56 #undef CONFIG_SHOW_BOOT_PROGRESS 57 58 #define CONFIG_ARCH_CPU_INIT 59 #define CONFIG_DISPLAY_CPUINFO 60 #define CONFIG_DISPLAY_BOARDINFO 61 #define CONFIG_BOARD_EARLY_INIT_F 62 #define CONFIG_USE_ARCH_MEMSET 63 #define CONFIG_USE_ARCH_MEMCPY 64 #define CONFIG_TMU_TIMER 65 66 /* STACK */ 67 #define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc 68 #define STACK_AREA_SIZE 0xC000 69 #define LOW_LEVEL_MERAM_STACK \ 70 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 71 72 /* MEMORY */ 73 #define LAGER_SDRAM_BASE 0x40000000 74 #define LAGER_SDRAM_SIZE (2048u * 1024 * 1024) 75 #define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 76 77 #define CONFIG_SYS_LONGHELP 78 #define CONFIG_SYS_CBSIZE 256 79 #define CONFIG_SYS_PBSIZE 256 80 #define CONFIG_SYS_MAXARGS 16 81 #define CONFIG_SYS_BARGSIZE 512 82 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } 83 84 /* SCIF */ 85 #define CONFIG_SCIF_CONSOLE 86 #define CONFIG_CONS_SCIF0 87 #define SCIF0_BASE 0xe6e60000 88 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 89 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 90 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 91 92 #define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE) 93 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 94 504 * 1024 * 1024) 95 #undef CONFIG_SYS_ALT_MEMTEST 96 #undef CONFIG_SYS_MEMTEST_SCRATCH 97 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 98 99 #define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE) 100 #define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE) 101 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) 102 #define CONFIG_NR_DRAM_BANKS 1 103 104 #define CONFIG_SYS_MONITOR_BASE 0x00000000 105 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 106 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 107 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 108 109 /* USE SPI */ 110 #define CONFIG_SPI 111 #define CONFIG_SPI_FLASH_BAR 112 #define CONFIG_SH_QSPI 113 #define CONFIG_SPI_FLASH 114 #define CONFIG_SPI_FLASH_SPANSION 115 #define CONFIG_SYS_NO_FLASH 116 117 /* ENV setting */ 118 #define CONFIG_ENV_IS_IN_SPI_FLASH 119 #define CONFIG_ENV_ADDR 0xC0000 120 121 /* Common ENV setting */ 122 #define CONFIG_ENV_OVERWRITE 123 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 124 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 125 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 126 #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) 127 128 /* SH Ether */ 129 #define CONFIG_NET_MULTI 130 #define CONFIG_SH_ETHER 131 #define CONFIG_SH_ETHER_USE_PORT 0 132 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 133 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 134 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 135 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 136 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 137 #define CONFIG_PHYLIB 138 #define CONFIG_PHY_MICREL 139 #define CONFIG_BITBANGMII 140 #define CONFIG_BITBANGMII_MULTI 141 142 /* I2C */ 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C_RCAR 145 #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 146 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 147 #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 148 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 149 #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 150 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 151 #define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 152 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 153 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 154 155 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 156 157 /* Board Clock */ 158 #define CONFIG_BASE_CLK_FREQ 20000000u 159 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ 160 #define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2) 161 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 162 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 163 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 164 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ 165 166 #define CONFIG_SYS_TMU_CLK_DIV 4 167 168 #endif /* __LAGER_H */ 169