1 /* 2 * include/configs/lager.h 3 * This file is lager board configuration. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __LAGER_H 11 #define __LAGER_H 12 13 #undef DEBUG 14 #define CONFIG_ARMV7 15 #define CONFIG_R8A7790 16 #define CONFIG_RMOBILE 17 #define CONFIG_RMOBILE_BOARD_STRING "Lager" 18 #define CONFIG_SH_GPIO_PFC 19 20 #include <asm/arch/rmobile.h> 21 22 #define CONFIG_CMD_EDITENV 23 #define CONFIG_CMD_SAVEENV 24 #define CONFIG_CMD_MEMORY 25 #define CONFIG_CMD_DFL 26 #define CONFIG_CMD_SDRAM 27 #define CONFIG_CMD_RUN 28 #define CONFIG_CMD_LOADS 29 #define CONFIG_CMD_NET 30 #define CONFIG_CMD_MII 31 #define CONFIG_CMD_PING 32 #define CONFIG_CMD_DHCP 33 #define CONFIG_CMD_NFS 34 #define CONFIG_CMD_BOOTZ 35 36 #define CONFIG_CMD_SF 37 #define CONFIG_CMD_SPI 38 #define CONFIG_SYS_TEXT_BASE 0xE8080000 39 40 #define CONFIG_CMDLINE_TAG 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_CMDLINE_EDITING 44 #define CONFIG_OF_LIBFDT 45 46 /* #define CONFIG_OF_LIBFDT */ 47 #define BOARD_LATE_INIT 48 49 #define CONFIG_BAUDRATE 38400 50 #define CONFIG_BOOTDELAY 3 51 #define CONFIG_BOOTARGS "" 52 53 #define CONFIG_VERSION_VARIABLE 54 #undef CONFIG_SHOW_BOOT_PROGRESS 55 56 #define CONFIG_ARCH_CPU_INIT 57 #define CONFIG_DISPLAY_CPUINFO 58 #define CONFIG_DISPLAY_BOARDINFO 59 #define CONFIG_BOARD_EARLY_INIT_F 60 #define CONFIG_TMU_TIMER 61 62 /* STACK */ 63 #define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc 64 #define STACK_AREA_SIZE 0xC000 65 #define LOW_LEVEL_MERAM_STACK \ 66 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 67 68 /* MEMORY */ 69 #define LAGER_SDRAM_BASE 0x40000000 70 #define LAGER_SDRAM_SIZE (2048u * 1024 * 1024) 71 #define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 72 73 #define CONFIG_SYS_LONGHELP 74 #define CONFIG_SYS_CBSIZE 256 75 #define CONFIG_SYS_PBSIZE 256 76 #define CONFIG_SYS_MAXARGS 16 77 #define CONFIG_SYS_BARGSIZE 512 78 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } 79 80 /* SCIF */ 81 #define CONFIG_SCIF_CONSOLE 82 #define CONFIG_CONS_SCIF0 83 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 84 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 85 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 86 87 #define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE) 88 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 89 504 * 1024 * 1024) 90 #undef CONFIG_SYS_ALT_MEMTEST 91 #undef CONFIG_SYS_MEMTEST_SCRATCH 92 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 93 94 #define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE) 95 #define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE) 96 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) 97 #define CONFIG_NR_DRAM_BANKS 1 98 99 #define CONFIG_SYS_MONITOR_BASE 0x00000000 100 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 101 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 102 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 103 104 /* USE SPI */ 105 #define CONFIG_SPI 106 #define CONFIG_SPI_FLASH_BAR 107 #define CONFIG_SH_QSPI 108 #define CONFIG_SPI_FLASH 109 #define CONFIG_SPI_FLASH_SPANSION 110 #define CONFIG_SYS_NO_FLASH 111 112 /* ENV setting */ 113 #define CONFIG_ENV_IS_IN_SPI_FLASH 114 #define CONFIG_ENV_ADDR 0xC0000 115 116 /* Common ENV setting */ 117 #define CONFIG_ENV_OVERWRITE 118 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 119 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 120 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 121 #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) 122 123 /* SH Ether */ 124 #define CONFIG_NET_MULTI 125 #define CONFIG_SH_ETHER 126 #define CONFIG_SH_ETHER_USE_PORT 0 127 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 128 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 129 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 130 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 131 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 132 #define CONFIG_PHYLIB 133 #define CONFIG_PHY_MICREL 134 #define CONFIG_BITBANGMII 135 #define CONFIG_BITBANGMII_MULTI 136 137 /* I2C */ 138 #define CONFIG_SYS_I2C 139 #define CONFIG_SYS_I2C_RCAR 140 #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 141 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 142 #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 143 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 144 #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 145 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 146 #define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 147 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 148 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 149 150 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 151 152 /* Board Clock */ 153 #define RMOBILE_XTAL_CLK 20000000u 154 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 155 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 156 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 157 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 158 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 159 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 160 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ 161 162 #define CONFIG_SYS_TMU_CLK_DIV 4 163 164 #endif /* __LAGER_H */ 165