1f4ec4522SNobuhiro Iwamatsu /* 2f4ec4522SNobuhiro Iwamatsu * include/configs/lager.h 3f4ec4522SNobuhiro Iwamatsu * This file is lager board configuration. 4f4ec4522SNobuhiro Iwamatsu * 55ca6dfe6SNobuhiro Iwamatsu * Copyright (C) 2013, 2014 Renesas Electronics Corporation 6f4ec4522SNobuhiro Iwamatsu * 7f4ec4522SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 8f4ec4522SNobuhiro Iwamatsu */ 9f4ec4522SNobuhiro Iwamatsu 10f4ec4522SNobuhiro Iwamatsu #ifndef __LAGER_H 11f4ec4522SNobuhiro Iwamatsu #define __LAGER_H 12f4ec4522SNobuhiro Iwamatsu 13f4ec4522SNobuhiro Iwamatsu #undef DEBUG 14f4ec4522SNobuhiro Iwamatsu #define CONFIG_R8A7790 15*1cc95f6eSNobuhiro Iwamatsu #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager" 16f4ec4522SNobuhiro Iwamatsu 175ca6dfe6SNobuhiro Iwamatsu #include "rcar-gen2-common.h" 18d80149b2SNobuhiro Iwamatsu 19*1cc95f6eSNobuhiro Iwamatsu #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 20fb6f6001SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0xB0000000 21fb6f6001SNobuhiro Iwamatsu #else 220e05b217SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0xE8080000 23fb6f6001SNobuhiro Iwamatsu #endif 24f4ec4522SNobuhiro Iwamatsu 25f4ec4522SNobuhiro Iwamatsu /* STACK */ 26fb6f6001SNobuhiro Iwamatsu #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 27fb6f6001SNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 28fb6f6001SNobuhiro Iwamatsu #else 29fb6f6001SNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 30fb6f6001SNobuhiro Iwamatsu #endif 31f4ec4522SNobuhiro Iwamatsu #define STACK_AREA_SIZE 0xC000 32f4ec4522SNobuhiro Iwamatsu #define LOW_LEVEL_MERAM_STACK \ 33f4ec4522SNobuhiro Iwamatsu (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34f4ec4522SNobuhiro Iwamatsu 35f4ec4522SNobuhiro Iwamatsu /* MEMORY */ 365ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_BASE 0x40000000 375ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 385ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39f4ec4522SNobuhiro Iwamatsu 40f4ec4522SNobuhiro Iwamatsu /* SCIF */ 41f4ec4522SNobuhiro Iwamatsu 425ca6dfe6SNobuhiro Iwamatsu /* SPI */ 430e05b217SNobuhiro Iwamatsu #define CONFIG_SPI 440e05b217SNobuhiro Iwamatsu 4523565c6bSNobuhiro Iwamatsu /* SH Ether */ 4623565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER 4723565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT 0 4823565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR 0x1 4923565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 5023565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 5123565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_WRITEBACK 5223565c6bSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_INVALIDATE 5323565c6bSNobuhiro Iwamatsu #define CONFIG_BITBANGMII 5423565c6bSNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 5523565c6bSNobuhiro Iwamatsu 56b9107adfSNobuhiro Iwamatsu /* I2C */ 57b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_I2C 58b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_RCAR 59b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 60b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 61b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 62b9107adfSNobuhiro Iwamatsu #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 63b9107adfSNobuhiro Iwamatsu #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 64b9107adfSNobuhiro Iwamatsu 65b9986be0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 66b9986be0SNobuhiro Iwamatsu 67f4ec4522SNobuhiro Iwamatsu /* Board Clock */ 68b1f78a2eSNobuhiro Iwamatsu #define RMOBILE_XTAL_CLK 20000000u 69b1f78a2eSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 70b1f78a2eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 71b1f78a2eSNobuhiro Iwamatsu #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 72f4ec4522SNobuhiro Iwamatsu #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 73f4ec4522SNobuhiro Iwamatsu #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 74b9107adfSNobuhiro Iwamatsu #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 75f4ec4522SNobuhiro Iwamatsu 76f4ec4522SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 77f4ec4522SNobuhiro Iwamatsu 785c4bb96eSNobuhiro Iwamatsu /* USB */ 795c4bb96eSNobuhiro Iwamatsu #define CONFIG_USB_EHCI_RMOBILE 805906fadeSNobuhiro Iwamatsu #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 815c4bb96eSNobuhiro Iwamatsu 82d7916b1dSNobuhiro Iwamatsu /* MMC */ 83d7916b1dSNobuhiro Iwamatsu #define CONFIG_SH_MMCIF 84d7916b1dSNobuhiro Iwamatsu #define CONFIG_SH_MMCIF_ADDR 0xEE220000 85d7916b1dSNobuhiro Iwamatsu #define CONFIG_SH_MMCIF_CLK 97500000 86d7916b1dSNobuhiro Iwamatsu 878e2e5886SNobuhiro Iwamatsu /* Module stop status bits */ 888e2e5886SNobuhiro Iwamatsu /* INTC-RT */ 898e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP0_ENA 0x00400000 908e2e5886SNobuhiro Iwamatsu /* MSIF */ 918e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP2_ENA 0x00002000 928e2e5886SNobuhiro Iwamatsu /* INTC-SYS, IRQC */ 938e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP4_ENA 0x00000180 948e2e5886SNobuhiro Iwamatsu /* SCIF0 */ 958e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP7_ENA 0x00200000 968e2e5886SNobuhiro Iwamatsu 97acdfecbbSNobuhiro Iwamatsu /* SDHI */ 98acdfecbbSNobuhiro Iwamatsu #define CONFIG_SH_SDHI_FREQ 97500000 99acdfecbbSNobuhiro Iwamatsu 100f4ec4522SNobuhiro Iwamatsu #endif /* __LAGER_H */ 101