xref: /rk3399_rockchip-uboot/include/configs/km/km_arm.h (revision ea616d4defbf90b1b0cbdf5d8425b574d606cd35)
1264eaa0eSValentin Longchamp /*
2264eaa0eSValentin Longchamp  * (C) Copyright 2009
3264eaa0eSValentin Longchamp  * Marvell Semiconductor <www.marvell.com>
4264eaa0eSValentin Longchamp  * Prafulla Wadaskar <prafulla@marvell.com>
5264eaa0eSValentin Longchamp  *
6264eaa0eSValentin Longchamp  * (C) Copyright 2009
7264eaa0eSValentin Longchamp  * Stefan Roese, DENX Software Engineering, sr@denx.de.
8264eaa0eSValentin Longchamp  *
9264eaa0eSValentin Longchamp  * (C) Copyright 2010-2011
10264eaa0eSValentin Longchamp  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11264eaa0eSValentin Longchamp  *
12264eaa0eSValentin Longchamp  * See file CREDITS for list of people who contributed to this
13264eaa0eSValentin Longchamp  * project.
14264eaa0eSValentin Longchamp  *
15264eaa0eSValentin Longchamp  * This program is free software; you can redistribute it and/or
16264eaa0eSValentin Longchamp  * modify it under the terms of the GNU General Public License as
17264eaa0eSValentin Longchamp  * published by the Free Software Foundation; either version 2 of
18264eaa0eSValentin Longchamp  * the License, or (at your option) any later version.
19264eaa0eSValentin Longchamp  *
20264eaa0eSValentin Longchamp  * This program is distributed in the hope that it will be useful,
21264eaa0eSValentin Longchamp  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22264eaa0eSValentin Longchamp  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23264eaa0eSValentin Longchamp  * GNU General Public License for more details.
24264eaa0eSValentin Longchamp  *
25264eaa0eSValentin Longchamp  * You should have received a copy of the GNU General Public License
26264eaa0eSValentin Longchamp  * along with this program; if not, write to the Free Software
27264eaa0eSValentin Longchamp  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28264eaa0eSValentin Longchamp  * MA 02110-1301 USA
29264eaa0eSValentin Longchamp  */
30264eaa0eSValentin Longchamp 
31264eaa0eSValentin Longchamp /*
32264eaa0eSValentin Longchamp  * for linking errors see
33264eaa0eSValentin Longchamp  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
34264eaa0eSValentin Longchamp  */
35264eaa0eSValentin Longchamp 
36264eaa0eSValentin Longchamp #ifndef _CONFIG_KM_ARM_H
37264eaa0eSValentin Longchamp #define _CONFIG_KM_ARM_H
38264eaa0eSValentin Longchamp 
39264eaa0eSValentin Longchamp /*
40264eaa0eSValentin Longchamp  * High Level Configuration Options (easy to change)
41264eaa0eSValentin Longchamp  */
42264eaa0eSValentin Longchamp #define CONFIG_MARVELL
43264eaa0eSValentin Longchamp #define CONFIG_ARM926EJS		/* Basic Architecture */
44264eaa0eSValentin Longchamp #define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
45264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD			/* SOC Family Name */
46264eaa0eSValentin Longchamp #define CONFIG_KW88F6281		/* SOC Name */
47264eaa0eSValentin Longchamp #define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */
48264eaa0eSValentin Longchamp 
49264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */
50264eaa0eSValentin Longchamp #include "keymile-common.h"
51264eaa0eSValentin Longchamp 
52264eaa0eSValentin Longchamp #define CONFIG_SYS_TEXT_BASE	0x04000000	/* code address after reloc */
53264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE		(128 << 10)	/* NAND chip block size	*/
54264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
55264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
56264eaa0eSValentin Longchamp #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
57264eaa0eSValentin Longchamp 
58264eaa0eSValentin Longchamp /* pseudo-non volatile RAM [hex] */
59264eaa0eSValentin Longchamp #define CONFIG_KM_PNVRAM	0x80000
60264eaa0eSValentin Longchamp /* physical RAM MTD size [hex] */
61264eaa0eSValentin Longchamp #define CONFIG_KM_PHRAM		0x17F000
62264eaa0eSValentin Longchamp 
63264eaa0eSValentin Longchamp #define CONFIG_KM_CRAMFS_ADDR	0x2400000
64264eaa0eSValentin Longchamp #define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 4096KBytes */
65264eaa0eSValentin Longchamp 
66264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV_CPU						\
67264eaa0eSValentin Longchamp 	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0"		\
68264eaa0eSValentin Longchamp 	"boot=bootm ${actual_kernel_addr} - -\0"			\
692d9528e3SHolger Brunck 	"cramfsloadfdt=true\0"						\
70264eaa0eSValentin Longchamp 	CONFIG_KM_DEF_ENV_UPDATE					\
71264eaa0eSValentin Longchamp 	""
72264eaa0eSValentin Longchamp 
732d9528e3SHolger Brunck #define CONFIG_KM_ARCH_DBG_FILE		"scripts/debug-arm-env.txt"
74264eaa0eSValentin Longchamp 
75264eaa0eSValentin Longchamp #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
76264eaa0eSValentin Longchamp #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
77264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
78264eaa0eSValentin Longchamp #undef  CONFIG_KIRKWOOD_PCIE_INIT	/* Disable PCIE Port0 for kernel */
79264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
80264eaa0eSValentin Longchamp 
81264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R
82264eaa0eSValentin Longchamp 
83264eaa0eSValentin Longchamp /*
84264eaa0eSValentin Longchamp  * NS16550 Configuration
85264eaa0eSValentin Longchamp  */
86264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550
87264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL
88264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
89264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
90264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
91264eaa0eSValentin Longchamp 
92264eaa0eSValentin Longchamp /*
93264eaa0eSValentin Longchamp  * Serial Port configuration
94264eaa0eSValentin Longchamp  * The following definitions let you select what serial you want to use
95264eaa0eSValentin Longchamp  * for your console driver.
96264eaa0eSValentin Longchamp  */
97264eaa0eSValentin Longchamp 
98264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX	1	/* Console on UART0 */
99264eaa0eSValentin Longchamp 
100264eaa0eSValentin Longchamp /*
101264eaa0eSValentin Longchamp  * For booting Linux, the board info and command line data
102264eaa0eSValentin Longchamp  * have to be in the first 8 MB of memory, since this is
103264eaa0eSValentin Longchamp  * the maximum mapped by the Linux kernel during initialization.
104264eaa0eSValentin Longchamp  */
105264eaa0eSValentin Longchamp #define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
106264eaa0eSValentin Longchamp #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
107264eaa0eSValentin Longchamp #define CONFIG_INITRD_TAG		/* enable INITRD tag */
108264eaa0eSValentin Longchamp #define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
109264eaa0eSValentin Longchamp 
110264eaa0eSValentin Longchamp /*
111264eaa0eSValentin Longchamp  * Commands configuration
112264eaa0eSValentin Longchamp  */
113264eaa0eSValentin Longchamp #define CONFIG_CMD_ELF
114264eaa0eSValentin Longchamp #define CONFIG_CMD_MTDPARTS
115264eaa0eSValentin Longchamp #define CONFIG_CMD_NAND
116264eaa0eSValentin Longchamp #define CONFIG_CMD_NFS
117264eaa0eSValentin Longchamp 
118264eaa0eSValentin Longchamp /*
119264eaa0eSValentin Longchamp  * Without NOR FLASH we need this
120264eaa0eSValentin Longchamp  */
121264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH
122264eaa0eSValentin Longchamp #undef CONFIG_CMD_FLASH
123264eaa0eSValentin Longchamp #undef CONFIG_CMD_IMLS
124264eaa0eSValentin Longchamp 
125264eaa0eSValentin Longchamp /*
126264eaa0eSValentin Longchamp  * NAND Flash configuration
127264eaa0eSValentin Longchamp  */
128264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE	1
129264eaa0eSValentin Longchamp #define NAND_MAX_CHIPS			1
130264eaa0eSValentin Longchamp #define CONFIG_NAND_KIRKWOOD
131264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE		0xd8000000
132264eaa0eSValentin Longchamp 
133264eaa0eSValentin Longchamp #define BOOTFLASH_START		0x0
134264eaa0eSValentin Longchamp 
135264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
136264eaa0eSValentin Longchamp 
137264eaa0eSValentin Longchamp /*
138264eaa0eSValentin Longchamp  * Other required minimal configurations
139264eaa0eSValentin Longchamp  */
140264eaa0eSValentin Longchamp #define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
141264eaa0eSValentin Longchamp #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
142264eaa0eSValentin Longchamp #define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
143264eaa0eSValentin Longchamp #define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
144264eaa0eSValentin Longchamp #define CONFIG_NR_DRAM_BANKS	4
145264eaa0eSValentin Longchamp #define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
146264eaa0eSValentin Longchamp #define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
147264eaa0eSValentin Longchamp 
148264eaa0eSValentin Longchamp /*
149264eaa0eSValentin Longchamp  * Ethernet Driver configuration
150264eaa0eSValentin Longchamp  */
151264eaa0eSValentin Longchamp #define CONFIG_NETCONSOLE	/* include NetConsole support   */
152264eaa0eSValentin Longchamp #define CONFIG_NET_MULTI	/* specify more that one ports available */
153264eaa0eSValentin Longchamp #define CONFIG_MII		/* expose smi ove miiphy interface */
154264eaa0eSValentin Longchamp #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
155264eaa0eSValentin Longchamp #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
156264eaa0eSValentin Longchamp #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
157264eaa0eSValentin Longchamp #define CONFIG_PHY_BASE_ADR	0
158264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
159264eaa0eSValentin Longchamp #define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
160264eaa0eSValentin Longchamp 
161264eaa0eSValentin Longchamp /*
162264eaa0eSValentin Longchamp  * UBI related stuff
163264eaa0eSValentin Longchamp  */
164264eaa0eSValentin Longchamp #define CONFIG_SYS_USE_UBI
165264eaa0eSValentin Longchamp 
166264eaa0eSValentin Longchamp /*
167264eaa0eSValentin Longchamp  * I2C related stuff
168264eaa0eSValentin Longchamp  */
169264eaa0eSValentin Longchamp #define	CONFIG_SOFT_I2C		/* I2C bit-banged	*/
170264eaa0eSValentin Longchamp 
171264eaa0eSValentin Longchamp #define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
172264eaa0eSValentin Longchamp #if defined(CONFIG_SOFT_I2C)
173264eaa0eSValentin Longchamp #ifndef __ASSEMBLY__
174264eaa0eSValentin Longchamp #include <asm/arch-kirkwood/gpio.h>
175264eaa0eSValentin Longchamp extern void __set_direction(unsigned pin, int high);
176264eaa0eSValentin Longchamp void set_sda(int state);
177264eaa0eSValentin Longchamp void set_scl(int state);
178264eaa0eSValentin Longchamp int get_sda(void);
179264eaa0eSValentin Longchamp int get_scl(void);
180264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SDA_PIN	8
181264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SCL_PIN	9
182264eaa0eSValentin Longchamp #define KM_KIRKWOOD_ENV_WP	38
183264eaa0eSValentin Longchamp 
184264eaa0eSValentin Longchamp #define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
185264eaa0eSValentin Longchamp #define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
186264eaa0eSValentin Longchamp #define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
187264eaa0eSValentin Longchamp #define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
188264eaa0eSValentin Longchamp #define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
189264eaa0eSValentin Longchamp #endif
190264eaa0eSValentin Longchamp 
191264eaa0eSValentin Longchamp #define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
192264eaa0eSValentin Longchamp #define I2C_SOFT_DECLARATIONS
193264eaa0eSValentin Longchamp 
194264eaa0eSValentin Longchamp #define	CONFIG_SYS_I2C_SLAVE		0x0
195264eaa0eSValentin Longchamp #define	CONFIG_SYS_I2C_SPEED		100000
196264eaa0eSValentin Longchamp #endif
197264eaa0eSValentin Longchamp 
198264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
199264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
200264eaa0eSValentin Longchamp 
201264eaa0eSValentin Longchamp /*
202264eaa0eSValentin Longchamp  *  Environment variables configurations
203264eaa0eSValentin Longchamp  */
204264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
205264eaa0eSValentin Longchamp #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
206264eaa0eSValentin Longchamp #define CONFIG_ENV_EEPROM_IS_ON_I2C
207264eaa0eSValentin Longchamp #define CONFIG_SYS_EEPROM_WREN
208264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
209264eaa0eSValentin Longchamp #undef	CONFIG_ENV_SIZE
210264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
211264eaa0eSValentin Longchamp #define CONFIG_I2C_ENV_EEPROM_BUS	"pca9547:70:d\0"
212264eaa0eSValentin Longchamp 
213264eaa0eSValentin Longchamp /* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
214264eaa0eSValentin Longchamp #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
215264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
216264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
217264eaa0eSValentin Longchamp 
218264eaa0eSValentin Longchamp #define CONFIG_CMD_SF
219264eaa0eSValentin Longchamp 
220264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH
221264eaa0eSValentin Longchamp #define CONFIG_HARD_SPI
222264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_SPI
223264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH_STMICRO
224264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_BUS		0
225264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_CS		0
226264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_MAX_HZ		50000000	/* 50Mhz */
227264eaa0eSValentin Longchamp 
228264eaa0eSValentin Longchamp #define FLASH_GPIO_PIN			0x00010000
229264eaa0eSValentin Longchamp 
230264eaa0eSValentin Longchamp #define MTDIDS_DEFAULT		"nand0=orion_nand"
231264eaa0eSValentin Longchamp /* test-only: partitioning needs some tuning, this is just for tests */
232264eaa0eSValentin Longchamp #define MTDPARTS_DEFAULT	"mtdparts="				\
233264eaa0eSValentin Longchamp 	"orion_nand:"							\
234264eaa0eSValentin Longchamp 		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
235264eaa0eSValentin Longchamp 
236264eaa0eSValentin Longchamp #define	CONFIG_KM_DEF_ENV_UPDATE					\
237264eaa0eSValentin Longchamp 	"update="							\
238264eaa0eSValentin Longchamp 		"spi on;sf probe 0;sf erase 0 50000;"			\
239264eaa0eSValentin Longchamp 		"sf write ${u-boot_addr_r} 0 ${filesize};"		\
240264eaa0eSValentin Longchamp 		"spi off\0"
241264eaa0eSValentin Longchamp 
242*ea616d4dSValentin Longchamp /*
243*ea616d4dSValentin Longchamp  * Default environment variables
244*ea616d4dSValentin Longchamp  */
245*ea616d4dSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS					\
246*ea616d4dSValentin Longchamp 	CONFIG_KM_DEF_ENV						\
247*ea616d4dSValentin Longchamp 	"newenv=setenv addr 0x100000 && "				\
248*ea616d4dSValentin Longchamp 		"i2c dev 1; mw.b ${addr} 0 4 && "			\
249*ea616d4dSValentin Longchamp 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
250*ea616d4dSValentin Longchamp 		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
251*ea616d4dSValentin Longchamp 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
252*ea616d4dSValentin Longchamp 		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
253*ea616d4dSValentin Longchamp 	"rootpath=/opt/eldk/arm\0"					\
254*ea616d4dSValentin Longchamp 	"EEprom_ivm=" KM_IVM_BUS "\0"					\
255*ea616d4dSValentin Longchamp 	""
256*ea616d4dSValentin Longchamp 
257264eaa0eSValentin Longchamp #if defined(CONFIG_SYS_NO_FLASH)
258264eaa0eSValentin Longchamp #define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
259264eaa0eSValentin Longchamp #undef	CONFIG_FLASH_CFI_MTD
260264eaa0eSValentin Longchamp #undef	CONFIG_JFFS2_CMDLINE
261264eaa0eSValentin Longchamp #endif
262264eaa0eSValentin Longchamp 
263264eaa0eSValentin Longchamp /* additions for new relocation code, must be added to all boards */
264264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE		0x00000000
265264eaa0eSValentin Longchamp /* Kirkwood has 2k of Security SRAM, use it for SP */
266264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
267264eaa0eSValentin Longchamp /* Do early setups now in board_init_f() */
268264eaa0eSValentin Longchamp #define CONFIG_BOARD_EARLY_INIT_F
269264eaa0eSValentin Longchamp 
270264eaa0eSValentin Longchamp /*
271264eaa0eSValentin Longchamp  * resereved pram area at the end of memroy [hex]
272264eaa0eSValentin Longchamp  * 8Mbytes for switch + 4Kbytes for bootcount
273264eaa0eSValentin Longchamp  */
274264eaa0eSValentin Longchamp #define CONFIG_KM_RESERVED_PRAM 0x801000
275264eaa0eSValentin Longchamp /* address for the bootcount (taken from end of RAM) */
276264eaa0eSValentin Longchamp #define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
277264eaa0eSValentin Longchamp 
278264eaa0eSValentin Longchamp #endif /* _CONFIG_KM_ARM_H */
279