1264eaa0eSValentin Longchamp /* 2264eaa0eSValentin Longchamp * (C) Copyright 2009 3264eaa0eSValentin Longchamp * Marvell Semiconductor <www.marvell.com> 4264eaa0eSValentin Longchamp * Prafulla Wadaskar <prafulla@marvell.com> 5264eaa0eSValentin Longchamp * 6264eaa0eSValentin Longchamp * (C) Copyright 2009 7264eaa0eSValentin Longchamp * Stefan Roese, DENX Software Engineering, sr@denx.de. 8264eaa0eSValentin Longchamp * 9264eaa0eSValentin Longchamp * (C) Copyright 2010-2011 10264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11264eaa0eSValentin Longchamp * 12264eaa0eSValentin Longchamp * See file CREDITS for list of people who contributed to this 13264eaa0eSValentin Longchamp * project. 14264eaa0eSValentin Longchamp * 15264eaa0eSValentin Longchamp * This program is free software; you can redistribute it and/or 16264eaa0eSValentin Longchamp * modify it under the terms of the GNU General Public License as 17264eaa0eSValentin Longchamp * published by the Free Software Foundation; either version 2 of 18264eaa0eSValentin Longchamp * the License, or (at your option) any later version. 19264eaa0eSValentin Longchamp * 20264eaa0eSValentin Longchamp * This program is distributed in the hope that it will be useful, 21264eaa0eSValentin Longchamp * but WITHOUT ANY WARRANTY; without even the implied warranty of 22264eaa0eSValentin Longchamp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23264eaa0eSValentin Longchamp * GNU General Public License for more details. 24264eaa0eSValentin Longchamp * 25264eaa0eSValentin Longchamp * You should have received a copy of the GNU General Public License 26264eaa0eSValentin Longchamp * along with this program; if not, write to the Free Software 27264eaa0eSValentin Longchamp * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28264eaa0eSValentin Longchamp * MA 02110-1301 USA 29264eaa0eSValentin Longchamp */ 30264eaa0eSValentin Longchamp 31264eaa0eSValentin Longchamp /* 32264eaa0eSValentin Longchamp * for linking errors see 33264eaa0eSValentin Longchamp * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html 34264eaa0eSValentin Longchamp */ 35264eaa0eSValentin Longchamp 36264eaa0eSValentin Longchamp #ifndef _CONFIG_KM_ARM_H 37264eaa0eSValentin Longchamp #define _CONFIG_KM_ARM_H 38264eaa0eSValentin Longchamp 39264eaa0eSValentin Longchamp /* 40264eaa0eSValentin Longchamp * High Level Configuration Options (easy to change) 41264eaa0eSValentin Longchamp */ 42264eaa0eSValentin Longchamp #define CONFIG_MARVELL 43264eaa0eSValentin Longchamp #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ 44264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD /* SOC Family Name */ 45264eaa0eSValentin Longchamp #define CONFIG_KW88F6281 /* SOC Name */ 46264eaa0eSValentin Longchamp #define CONFIG_MACH_KM_KIRKWOOD /* Machine type */ 47264eaa0eSValentin Longchamp 48264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 49264eaa0eSValentin Longchamp #include "keymile-common.h" 50264eaa0eSValentin Longchamp 51b5befd82SHolger Brunck #define CONFIG_CMD_NAND 52b5befd82SHolger Brunck #define CONFIG_CMD_SF 53b5befd82SHolger Brunck #define CONFIG_SOFT_I2C /* I2C bit-banged */ 54b5befd82SHolger Brunck 55b5befd82SHolger Brunck #include "asm/arch/config.h" 56b5befd82SHolger Brunck 57264eaa0eSValentin Longchamp #define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ 58264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ 59264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ 60264eaa0eSValentin Longchamp #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 61264eaa0eSValentin Longchamp 62264eaa0eSValentin Longchamp /* pseudo-non volatile RAM [hex] */ 63264eaa0eSValentin Longchamp #define CONFIG_KM_PNVRAM 0x80000 64264eaa0eSValentin Longchamp /* physical RAM MTD size [hex] */ 65264eaa0eSValentin Longchamp #define CONFIG_KM_PHRAM 0x17F000 66264eaa0eSValentin Longchamp 67264eaa0eSValentin Longchamp #define CONFIG_KM_CRAMFS_ADDR 0x2400000 68264eaa0eSValentin Longchamp #define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ 69264eaa0eSValentin Longchamp 70db0bb572SHolger Brunck /* architecture specific default bootargs */ 71db0bb572SHolger Brunck #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ 72db0bb572SHolger Brunck "bootcountaddr=${bootcountaddr} ${mtdparts}" 73db0bb572SHolger Brunck 74264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV_CPU \ 75db0bb572SHolger Brunck "boot=bootm ${load_addr_r} - -\0" \ 762d9528e3SHolger Brunck "cramfsloadfdt=true\0" \ 77264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV_UPDATE \ 78264eaa0eSValentin Longchamp "" 79264eaa0eSValentin Longchamp 80264eaa0eSValentin Longchamp #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 81264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 82264eaa0eSValentin Longchamp 83264eaa0eSValentin Longchamp /* 84264eaa0eSValentin Longchamp * NS16550 Configuration 85264eaa0eSValentin Longchamp */ 86264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550 87264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 88264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE (-4) 89264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 90264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE 913d3c7096SHolger Brunck #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE 92264eaa0eSValentin Longchamp 93264eaa0eSValentin Longchamp /* 94264eaa0eSValentin Longchamp * Serial Port configuration 95264eaa0eSValentin Longchamp * The following definitions let you select what serial you want to use 96264eaa0eSValentin Longchamp * for your console driver. 97264eaa0eSValentin Longchamp */ 98264eaa0eSValentin Longchamp 99264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX 1 /* Console on UART0 */ 100264eaa0eSValentin Longchamp 101264eaa0eSValentin Longchamp /* 102264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 103264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 104264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 105264eaa0eSValentin Longchamp */ 106264eaa0eSValentin Longchamp #define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */ 107264eaa0eSValentin Longchamp #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 108264eaa0eSValentin Longchamp #define CONFIG_INITRD_TAG /* enable INITRD tag */ 109264eaa0eSValentin Longchamp #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ 110264eaa0eSValentin Longchamp 111264eaa0eSValentin Longchamp /* 112264eaa0eSValentin Longchamp * Commands configuration 113264eaa0eSValentin Longchamp */ 114264eaa0eSValentin Longchamp #define CONFIG_CMD_ELF 115264eaa0eSValentin Longchamp #define CONFIG_CMD_MTDPARTS 116264eaa0eSValentin Longchamp #define CONFIG_CMD_NFS 117264eaa0eSValentin Longchamp 118264eaa0eSValentin Longchamp /* 119264eaa0eSValentin Longchamp * Without NOR FLASH we need this 120264eaa0eSValentin Longchamp */ 121264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH 122264eaa0eSValentin Longchamp #undef CONFIG_CMD_FLASH 123264eaa0eSValentin Longchamp #undef CONFIG_CMD_IMLS 124264eaa0eSValentin Longchamp 125264eaa0eSValentin Longchamp /* 126264eaa0eSValentin Longchamp * NAND Flash configuration 127264eaa0eSValentin Longchamp */ 128264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 129264eaa0eSValentin Longchamp #define NAND_MAX_CHIPS 1 130264eaa0eSValentin Longchamp 131264eaa0eSValentin Longchamp #define BOOTFLASH_START 0x0 132264eaa0eSValentin Longchamp 1333d3c7096SHolger Brunck /* Kirkwood has two serial IF */ 1343d3c7096SHolger Brunck #if (CONFIG_CONS_INDEX == 2) 1353d3c7096SHolger Brunck #define CONFIG_KM_CONSOLE_TTY "ttyS1" 1363d3c7096SHolger Brunck #else 137264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 1383d3c7096SHolger Brunck #endif 139264eaa0eSValentin Longchamp 140264eaa0eSValentin Longchamp /* 141264eaa0eSValentin Longchamp * Other required minimal configurations 142264eaa0eSValentin Longchamp */ 143264eaa0eSValentin Longchamp #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 144264eaa0eSValentin Longchamp #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 145264eaa0eSValentin Longchamp #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 146264eaa0eSValentin Longchamp #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 147264eaa0eSValentin Longchamp #define CONFIG_NR_DRAM_BANKS 4 148264eaa0eSValentin Longchamp #define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ 149264eaa0eSValentin Longchamp #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 150264eaa0eSValentin Longchamp 151264eaa0eSValentin Longchamp /* 152264eaa0eSValentin Longchamp * Ethernet Driver configuration 153264eaa0eSValentin Longchamp */ 154264eaa0eSValentin Longchamp #define CONFIG_NETCONSOLE /* include NetConsole support */ 155264eaa0eSValentin Longchamp #define CONFIG_NET_MULTI /* specify more that one ports available */ 156264eaa0eSValentin Longchamp #define CONFIG_MII /* expose smi ove miiphy interface */ 157264eaa0eSValentin Longchamp #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 158264eaa0eSValentin Longchamp #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 159264eaa0eSValentin Longchamp #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ 160264eaa0eSValentin Longchamp #define CONFIG_PHY_BASE_ADR 0 161264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 162264eaa0eSValentin Longchamp #define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */ 163264eaa0eSValentin Longchamp 164264eaa0eSValentin Longchamp /* 165264eaa0eSValentin Longchamp * UBI related stuff 166264eaa0eSValentin Longchamp */ 167264eaa0eSValentin Longchamp #define CONFIG_SYS_USE_UBI 168264eaa0eSValentin Longchamp 169264eaa0eSValentin Longchamp /* 170264eaa0eSValentin Longchamp * I2C related stuff 171264eaa0eSValentin Longchamp */ 172264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ 173264eaa0eSValentin Longchamp #if defined(CONFIG_SOFT_I2C) 174264eaa0eSValentin Longchamp #ifndef __ASSEMBLY__ 175264eaa0eSValentin Longchamp #include <asm/arch-kirkwood/gpio.h> 176264eaa0eSValentin Longchamp extern void __set_direction(unsigned pin, int high); 177264eaa0eSValentin Longchamp void set_sda(int state); 178264eaa0eSValentin Longchamp void set_scl(int state); 179264eaa0eSValentin Longchamp int get_sda(void); 180264eaa0eSValentin Longchamp int get_scl(void); 181264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SDA_PIN 8 182264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SCL_PIN 9 183264eaa0eSValentin Longchamp #define KM_KIRKWOOD_ENV_WP 38 184264eaa0eSValentin Longchamp 185264eaa0eSValentin Longchamp #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) 186264eaa0eSValentin Longchamp #define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) 187264eaa0eSValentin Longchamp #define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) 188264eaa0eSValentin Longchamp #define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) 189264eaa0eSValentin Longchamp #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) 190264eaa0eSValentin Longchamp #endif 191264eaa0eSValentin Longchamp 192264eaa0eSValentin Longchamp #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ 193264eaa0eSValentin Longchamp #define I2C_SOFT_DECLARATIONS 194264eaa0eSValentin Longchamp 195264eaa0eSValentin Longchamp #endif 196264eaa0eSValentin Longchamp 197264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 198264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 199264eaa0eSValentin Longchamp 200264eaa0eSValentin Longchamp /* 201264eaa0eSValentin Longchamp * Environment variables configurations 202264eaa0eSValentin Longchamp */ 203264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ 204264eaa0eSValentin Longchamp #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 205264eaa0eSValentin Longchamp #define CONFIG_ENV_EEPROM_IS_ON_I2C 206264eaa0eSValentin Longchamp #define CONFIG_SYS_EEPROM_WREN 207264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ 208264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) 209680cfaf8SValentin Longchamp #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" 210264eaa0eSValentin Longchamp 211264eaa0eSValentin Longchamp /* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 212264eaa0eSValentin Longchamp #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 213264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ 214264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 215264eaa0eSValentin Longchamp 216264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH 217264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH_STMICRO 218264eaa0eSValentin Longchamp 219264eaa0eSValentin Longchamp #define FLASH_GPIO_PIN 0x00010000 220264eaa0eSValentin Longchamp 221264eaa0eSValentin Longchamp #define MTDIDS_DEFAULT "nand0=orion_nand" 222264eaa0eSValentin Longchamp /* test-only: partitioning needs some tuning, this is just for tests */ 223264eaa0eSValentin Longchamp #define MTDPARTS_DEFAULT "mtdparts=" \ 224264eaa0eSValentin Longchamp "orion_nand:" \ 225264eaa0eSValentin Longchamp "-(" CONFIG_KM_UBI_PARTITION_NAME ")" 226264eaa0eSValentin Longchamp 227264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV_UPDATE \ 228264eaa0eSValentin Longchamp "update=" \ 229264eaa0eSValentin Longchamp "spi on;sf probe 0;sf erase 0 50000;" \ 230db0bb572SHolger Brunck "sf write ${load_addr_r} 0 ${filesize};" \ 231264eaa0eSValentin Longchamp "spi off\0" 232264eaa0eSValentin Longchamp 233ea616d4dSValentin Longchamp /* 234ea616d4dSValentin Longchamp * Default environment variables 235ea616d4dSValentin Longchamp */ 236ea616d4dSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 237ea616d4dSValentin Longchamp CONFIG_KM_DEF_ENV \ 238ea616d4dSValentin Longchamp "newenv=setenv addr 0x100000 && " \ 239ea616d4dSValentin Longchamp "i2c dev 1; mw.b ${addr} 0 4 && " \ 240ea616d4dSValentin Longchamp "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ 241ea616d4dSValentin Longchamp " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ 242ea616d4dSValentin Longchamp "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ 243ea616d4dSValentin Longchamp " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ 244*b648bfc2SHolger Brunck "arch=arm\0" \ 245ea616d4dSValentin Longchamp "EEprom_ivm=" KM_IVM_BUS "\0" \ 246ea616d4dSValentin Longchamp "" 247ea616d4dSValentin Longchamp 248264eaa0eSValentin Longchamp #if defined(CONFIG_SYS_NO_FLASH) 249264eaa0eSValentin Longchamp #define CONFIG_KM_UBI_PARTITION_NAME "ubi0" 250264eaa0eSValentin Longchamp #undef CONFIG_FLASH_CFI_MTD 25195e39793SValentin Longchamp #undef CONFIG_CMD_JFFS2 252264eaa0eSValentin Longchamp #undef CONFIG_JFFS2_CMDLINE 253264eaa0eSValentin Longchamp #endif 254264eaa0eSValentin Longchamp 255264eaa0eSValentin Longchamp /* additions for new relocation code, must be added to all boards */ 256264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE 0x00000000 257264eaa0eSValentin Longchamp /* Do early setups now in board_init_f() */ 258264eaa0eSValentin Longchamp #define CONFIG_BOARD_EARLY_INIT_F 259264eaa0eSValentin Longchamp 260264eaa0eSValentin Longchamp /* 261264eaa0eSValentin Longchamp * resereved pram area at the end of memroy [hex] 262264eaa0eSValentin Longchamp * 8Mbytes for switch + 4Kbytes for bootcount 263264eaa0eSValentin Longchamp */ 264264eaa0eSValentin Longchamp #define CONFIG_KM_RESERVED_PRAM 0x801000 265264eaa0eSValentin Longchamp /* address for the bootcount (taken from end of RAM) */ 266264eaa0eSValentin Longchamp #define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) 267264eaa0eSValentin Longchamp 268264eaa0eSValentin Longchamp #endif /* _CONFIG_KM_ARM_H */ 269