xref: /rk3399_rockchip-uboot/include/configs/km/km_arm.h (revision 264eaa0ea967bac32214b87d60cfc86c8b22cac6)
1*264eaa0eSValentin Longchamp /*
2*264eaa0eSValentin Longchamp  * (C) Copyright 2009
3*264eaa0eSValentin Longchamp  * Marvell Semiconductor <www.marvell.com>
4*264eaa0eSValentin Longchamp  * Prafulla Wadaskar <prafulla@marvell.com>
5*264eaa0eSValentin Longchamp  *
6*264eaa0eSValentin Longchamp  * (C) Copyright 2009
7*264eaa0eSValentin Longchamp  * Stefan Roese, DENX Software Engineering, sr@denx.de.
8*264eaa0eSValentin Longchamp  *
9*264eaa0eSValentin Longchamp  * (C) Copyright 2010-2011
10*264eaa0eSValentin Longchamp  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11*264eaa0eSValentin Longchamp  *
12*264eaa0eSValentin Longchamp  * See file CREDITS for list of people who contributed to this
13*264eaa0eSValentin Longchamp  * project.
14*264eaa0eSValentin Longchamp  *
15*264eaa0eSValentin Longchamp  * This program is free software; you can redistribute it and/or
16*264eaa0eSValentin Longchamp  * modify it under the terms of the GNU General Public License as
17*264eaa0eSValentin Longchamp  * published by the Free Software Foundation; either version 2 of
18*264eaa0eSValentin Longchamp  * the License, or (at your option) any later version.
19*264eaa0eSValentin Longchamp  *
20*264eaa0eSValentin Longchamp  * This program is distributed in the hope that it will be useful,
21*264eaa0eSValentin Longchamp  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22*264eaa0eSValentin Longchamp  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23*264eaa0eSValentin Longchamp  * GNU General Public License for more details.
24*264eaa0eSValentin Longchamp  *
25*264eaa0eSValentin Longchamp  * You should have received a copy of the GNU General Public License
26*264eaa0eSValentin Longchamp  * along with this program; if not, write to the Free Software
27*264eaa0eSValentin Longchamp  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28*264eaa0eSValentin Longchamp  * MA 02110-1301 USA
29*264eaa0eSValentin Longchamp  */
30*264eaa0eSValentin Longchamp 
31*264eaa0eSValentin Longchamp /*
32*264eaa0eSValentin Longchamp  * for linking errors see
33*264eaa0eSValentin Longchamp  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
34*264eaa0eSValentin Longchamp  */
35*264eaa0eSValentin Longchamp 
36*264eaa0eSValentin Longchamp #ifndef _CONFIG_KM_ARM_H
37*264eaa0eSValentin Longchamp #define _CONFIG_KM_ARM_H
38*264eaa0eSValentin Longchamp 
39*264eaa0eSValentin Longchamp /*
40*264eaa0eSValentin Longchamp  * High Level Configuration Options (easy to change)
41*264eaa0eSValentin Longchamp  */
42*264eaa0eSValentin Longchamp #define CONFIG_MARVELL
43*264eaa0eSValentin Longchamp #define CONFIG_ARM926EJS		/* Basic Architecture */
44*264eaa0eSValentin Longchamp #define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
45*264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD			/* SOC Family Name */
46*264eaa0eSValentin Longchamp #define CONFIG_KW88F6281		/* SOC Name */
47*264eaa0eSValentin Longchamp #define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */
48*264eaa0eSValentin Longchamp 
49*264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */
50*264eaa0eSValentin Longchamp #include "keymile-common.h"
51*264eaa0eSValentin Longchamp 
52*264eaa0eSValentin Longchamp #define CONFIG_SYS_TEXT_BASE	0x04000000	/* code address after reloc */
53*264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE		(128 << 10)	/* NAND chip block size	*/
54*264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
55*264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
56*264eaa0eSValentin Longchamp #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
57*264eaa0eSValentin Longchamp 
58*264eaa0eSValentin Longchamp /* pseudo-non volatile RAM [hex] */
59*264eaa0eSValentin Longchamp #define CONFIG_KM_PNVRAM	0x80000
60*264eaa0eSValentin Longchamp /* physical RAM MTD size [hex] */
61*264eaa0eSValentin Longchamp #define CONFIG_KM_PHRAM		0x17F000
62*264eaa0eSValentin Longchamp 
63*264eaa0eSValentin Longchamp #define CONFIG_KM_CRAMFS_ADDR	0x2400000
64*264eaa0eSValentin Longchamp #define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 4096KBytes */
65*264eaa0eSValentin Longchamp 
66*264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV_CPU						\
67*264eaa0eSValentin Longchamp 	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0"		\
68*264eaa0eSValentin Longchamp 	"boot=bootm ${actual_kernel_addr} - -\0"			\
69*264eaa0eSValentin Longchamp 	"cramfsloadfdt=echo \\\\c\0"					\
70*264eaa0eSValentin Longchamp 	"tftpfdt=echo \\\\c\0"						\
71*264eaa0eSValentin Longchamp 	CONFIG_KM_DEF_ENV_UPDATE					\
72*264eaa0eSValentin Longchamp 	""
73*264eaa0eSValentin Longchamp 
74*264eaa0eSValentin Longchamp 
75*264eaa0eSValentin Longchamp 
76*264eaa0eSValentin Longchamp #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
77*264eaa0eSValentin Longchamp #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
78*264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
79*264eaa0eSValentin Longchamp #undef  CONFIG_KIRKWOOD_PCIE_INIT	/* Disable PCIE Port0 for kernel */
80*264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
81*264eaa0eSValentin Longchamp 
82*264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R
83*264eaa0eSValentin Longchamp 
84*264eaa0eSValentin Longchamp /*
85*264eaa0eSValentin Longchamp  * NS16550 Configuration
86*264eaa0eSValentin Longchamp  */
87*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550
88*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL
89*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
90*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
91*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
92*264eaa0eSValentin Longchamp 
93*264eaa0eSValentin Longchamp /*
94*264eaa0eSValentin Longchamp  * Serial Port configuration
95*264eaa0eSValentin Longchamp  * The following definitions let you select what serial you want to use
96*264eaa0eSValentin Longchamp  * for your console driver.
97*264eaa0eSValentin Longchamp  */
98*264eaa0eSValentin Longchamp 
99*264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX	1	/* Console on UART0 */
100*264eaa0eSValentin Longchamp 
101*264eaa0eSValentin Longchamp /*
102*264eaa0eSValentin Longchamp  * For booting Linux, the board info and command line data
103*264eaa0eSValentin Longchamp  * have to be in the first 8 MB of memory, since this is
104*264eaa0eSValentin Longchamp  * the maximum mapped by the Linux kernel during initialization.
105*264eaa0eSValentin Longchamp  */
106*264eaa0eSValentin Longchamp #define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
107*264eaa0eSValentin Longchamp #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
108*264eaa0eSValentin Longchamp #define CONFIG_INITRD_TAG		/* enable INITRD tag */
109*264eaa0eSValentin Longchamp #define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
110*264eaa0eSValentin Longchamp 
111*264eaa0eSValentin Longchamp /*
112*264eaa0eSValentin Longchamp  * Commands configuration
113*264eaa0eSValentin Longchamp  */
114*264eaa0eSValentin Longchamp #define CONFIG_CMD_ELF
115*264eaa0eSValentin Longchamp #define CONFIG_CMD_MTDPARTS
116*264eaa0eSValentin Longchamp #define CONFIG_CMD_NAND
117*264eaa0eSValentin Longchamp #define CONFIG_CMD_NFS
118*264eaa0eSValentin Longchamp 
119*264eaa0eSValentin Longchamp /*
120*264eaa0eSValentin Longchamp  * Without NOR FLASH we need this
121*264eaa0eSValentin Longchamp  */
122*264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH
123*264eaa0eSValentin Longchamp #undef CONFIG_CMD_FLASH
124*264eaa0eSValentin Longchamp #undef CONFIG_CMD_IMLS
125*264eaa0eSValentin Longchamp 
126*264eaa0eSValentin Longchamp /*
127*264eaa0eSValentin Longchamp  * NAND Flash configuration
128*264eaa0eSValentin Longchamp  */
129*264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE	1
130*264eaa0eSValentin Longchamp #define NAND_MAX_CHIPS			1
131*264eaa0eSValentin Longchamp #define CONFIG_NAND_KIRKWOOD
132*264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE		0xd8000000
133*264eaa0eSValentin Longchamp 
134*264eaa0eSValentin Longchamp #define BOOTFLASH_START		0x0
135*264eaa0eSValentin Longchamp 
136*264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
137*264eaa0eSValentin Longchamp 
138*264eaa0eSValentin Longchamp /* size in bytes reserved for initial data */
139*264eaa0eSValentin Longchamp 
140*264eaa0eSValentin Longchamp /*
141*264eaa0eSValentin Longchamp  * Other required minimal configurations
142*264eaa0eSValentin Longchamp  */
143*264eaa0eSValentin Longchamp #define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
144*264eaa0eSValentin Longchamp #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
145*264eaa0eSValentin Longchamp #define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
146*264eaa0eSValentin Longchamp #define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
147*264eaa0eSValentin Longchamp #define CONFIG_NR_DRAM_BANKS	4
148*264eaa0eSValentin Longchamp #define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
149*264eaa0eSValentin Longchamp #define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
150*264eaa0eSValentin Longchamp 
151*264eaa0eSValentin Longchamp /*
152*264eaa0eSValentin Longchamp  * Ethernet Driver configuration
153*264eaa0eSValentin Longchamp  */
154*264eaa0eSValentin Longchamp #define CONFIG_NETCONSOLE	/* include NetConsole support   */
155*264eaa0eSValentin Longchamp #define CONFIG_NET_MULTI	/* specify more that one ports available */
156*264eaa0eSValentin Longchamp #define CONFIG_MII		/* expose smi ove miiphy interface */
157*264eaa0eSValentin Longchamp #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
158*264eaa0eSValentin Longchamp #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
159*264eaa0eSValentin Longchamp #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
160*264eaa0eSValentin Longchamp #define CONFIG_PHY_BASE_ADR	0
161*264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
162*264eaa0eSValentin Longchamp #define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
163*264eaa0eSValentin Longchamp 
164*264eaa0eSValentin Longchamp /*
165*264eaa0eSValentin Longchamp  * UBI related stuff
166*264eaa0eSValentin Longchamp  */
167*264eaa0eSValentin Longchamp #define CONFIG_SYS_USE_UBI
168*264eaa0eSValentin Longchamp 
169*264eaa0eSValentin Longchamp /*
170*264eaa0eSValentin Longchamp  * I2C related stuff
171*264eaa0eSValentin Longchamp  */
172*264eaa0eSValentin Longchamp #define	CONFIG_SOFT_I2C		/* I2C bit-banged	*/
173*264eaa0eSValentin Longchamp 
174*264eaa0eSValentin Longchamp #define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
175*264eaa0eSValentin Longchamp #if defined(CONFIG_SOFT_I2C)
176*264eaa0eSValentin Longchamp #ifndef __ASSEMBLY__
177*264eaa0eSValentin Longchamp #include <asm/arch-kirkwood/gpio.h>
178*264eaa0eSValentin Longchamp extern void __set_direction(unsigned pin, int high);
179*264eaa0eSValentin Longchamp void set_sda(int state);
180*264eaa0eSValentin Longchamp void set_scl(int state);
181*264eaa0eSValentin Longchamp int get_sda(void);
182*264eaa0eSValentin Longchamp int get_scl(void);
183*264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SDA_PIN	8
184*264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SCL_PIN	9
185*264eaa0eSValentin Longchamp #define KM_KIRKWOOD_ENV_WP	38
186*264eaa0eSValentin Longchamp 
187*264eaa0eSValentin Longchamp #define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
188*264eaa0eSValentin Longchamp #define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
189*264eaa0eSValentin Longchamp #define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
190*264eaa0eSValentin Longchamp #define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
191*264eaa0eSValentin Longchamp #define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
192*264eaa0eSValentin Longchamp #endif
193*264eaa0eSValentin Longchamp 
194*264eaa0eSValentin Longchamp #define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
195*264eaa0eSValentin Longchamp #define I2C_SOFT_DECLARATIONS
196*264eaa0eSValentin Longchamp 
197*264eaa0eSValentin Longchamp #define	CONFIG_SYS_I2C_SLAVE		0x0
198*264eaa0eSValentin Longchamp #define	CONFIG_SYS_I2C_SPEED		100000
199*264eaa0eSValentin Longchamp #endif
200*264eaa0eSValentin Longchamp 
201*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
202*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
203*264eaa0eSValentin Longchamp 
204*264eaa0eSValentin Longchamp /*
205*264eaa0eSValentin Longchamp  *  Environment variables configurations
206*264eaa0eSValentin Longchamp  */
207*264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
208*264eaa0eSValentin Longchamp #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
209*264eaa0eSValentin Longchamp #define CONFIG_ENV_EEPROM_IS_ON_I2C
210*264eaa0eSValentin Longchamp #define CONFIG_SYS_EEPROM_WREN
211*264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
212*264eaa0eSValentin Longchamp #undef	CONFIG_ENV_SIZE
213*264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
214*264eaa0eSValentin Longchamp #define CONFIG_I2C_ENV_EEPROM_BUS	"pca9547:70:d\0"
215*264eaa0eSValentin Longchamp 
216*264eaa0eSValentin Longchamp /* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
217*264eaa0eSValentin Longchamp #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
218*264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
219*264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
220*264eaa0eSValentin Longchamp 
221*264eaa0eSValentin Longchamp #define CONFIG_CMD_SF
222*264eaa0eSValentin Longchamp 
223*264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH
224*264eaa0eSValentin Longchamp #define CONFIG_HARD_SPI
225*264eaa0eSValentin Longchamp #define CONFIG_KIRKWOOD_SPI
226*264eaa0eSValentin Longchamp #define CONFIG_SPI_FLASH_STMICRO
227*264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_BUS		0
228*264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_CS		0
229*264eaa0eSValentin Longchamp #define CONFIG_ENV_SPI_MAX_HZ		50000000	/* 50Mhz */
230*264eaa0eSValentin Longchamp 
231*264eaa0eSValentin Longchamp #define FLASH_GPIO_PIN			0x00010000
232*264eaa0eSValentin Longchamp 
233*264eaa0eSValentin Longchamp #define MTDIDS_DEFAULT		"nand0=orion_nand"
234*264eaa0eSValentin Longchamp /* test-only: partitioning needs some tuning, this is just for tests */
235*264eaa0eSValentin Longchamp #define MTDPARTS_DEFAULT	"mtdparts="				\
236*264eaa0eSValentin Longchamp 	"orion_nand:"							\
237*264eaa0eSValentin Longchamp 		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
238*264eaa0eSValentin Longchamp 
239*264eaa0eSValentin Longchamp #define	CONFIG_KM_DEF_ENV_UPDATE					\
240*264eaa0eSValentin Longchamp 	"update="							\
241*264eaa0eSValentin Longchamp 		"spi on;sf probe 0;sf erase 0 50000;"			\
242*264eaa0eSValentin Longchamp 		"sf write ${u-boot_addr_r} 0 ${filesize};"		\
243*264eaa0eSValentin Longchamp 		"spi off\0"
244*264eaa0eSValentin Longchamp 
245*264eaa0eSValentin Longchamp #if defined(CONFIG_SYS_NO_FLASH)
246*264eaa0eSValentin Longchamp #define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
247*264eaa0eSValentin Longchamp #undef	CONFIG_FLASH_CFI_MTD
248*264eaa0eSValentin Longchamp #undef	CONFIG_JFFS2_CMDLINE
249*264eaa0eSValentin Longchamp #endif
250*264eaa0eSValentin Longchamp 
251*264eaa0eSValentin Longchamp /* additions for new relocation code, must be added to all boards */
252*264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE		0x00000000
253*264eaa0eSValentin Longchamp /* Kirkwood has 2k of Security SRAM, use it for SP */
254*264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
255*264eaa0eSValentin Longchamp /* Do early setups now in board_init_f() */
256*264eaa0eSValentin Longchamp #define CONFIG_BOARD_EARLY_INIT_F
257*264eaa0eSValentin Longchamp 
258*264eaa0eSValentin Longchamp /*
259*264eaa0eSValentin Longchamp  * resereved pram area at the end of memroy [hex]
260*264eaa0eSValentin Longchamp  * 8Mbytes for switch + 4Kbytes for bootcount
261*264eaa0eSValentin Longchamp  */
262*264eaa0eSValentin Longchamp #define CONFIG_KM_RESERVED_PRAM 0x801000
263*264eaa0eSValentin Longchamp /* address for the bootcount (taken from end of RAM) */
264*264eaa0eSValentin Longchamp #define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
265*264eaa0eSValentin Longchamp 
266*264eaa0eSValentin Longchamp #endif /* _CONFIG_KM_ARM_H */
267