1 /* 2 * (C) Copyright 2010 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 */ 10 11 #ifndef __CONFIG_KM83XX_H 12 #define __CONFIG_KM83XX_H 13 14 /* include common defines/options for all Keymile boards */ 15 #include "keymile-common.h" 16 #include "km-powerpc.h" 17 18 #ifndef MTDIDS_DEFAULT 19 # define MTDIDS_DEFAULT "nor0=boot" 20 #endif /* MTDIDS_DEFAULT */ 21 22 #ifndef MTDPARTS_DEFAULT 23 # define MTDPARTS_DEFAULT "mtdparts=" \ 24 "boot:" \ 25 "768k(u-boot)," \ 26 "128k(env)," \ 27 "128k(envred)," \ 28 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 29 #endif /* MTDPARTS_DEFAULT */ 30 31 #define CONFIG_MISC_INIT_R 32 /* 33 * System Clock Setup 34 */ 35 #define CONFIG_83XX_CLKIN 66000000 36 #define CONFIG_SYS_CLK_FREQ 66000000 37 #define CONFIG_83XX_PCICLK 66000000 38 39 /* 40 * IMMR new address 41 */ 42 #define CONFIG_SYS_IMMR 0xE0000000 43 44 /* 45 * Bus Arbitration Configuration Register (ACR) 46 */ 47 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 48 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 49 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 50 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 51 52 /* 53 * DDR Setup 54 */ 55 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 58 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 59 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 60 61 #define CFG_83XX_DDR_USES_CS0 62 63 /* 64 * Manually set up DDR parameters 65 */ 66 #define CONFIG_DDR_II 67 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 68 69 /* 70 * The reserved memory 71 */ 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 73 #define CONFIG_SYS_FLASH_BASE 0xF0000000 74 75 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 76 #define CONFIG_SYS_RAMBOOT 77 #endif 78 79 /* Reserve 768 kB for Mon */ 80 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 81 82 /* 83 * Initial RAM Base Address Setup 84 */ 85 #define CONFIG_SYS_INIT_RAM_LOCK 86 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 87 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 88 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 89 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 90 GENERATED_GBL_DATA_SIZE) 91 92 /* 93 * Init Local Bus Memory Controller: 94 * 95 * Bank Bus Machine PortSz Size Device 96 * ---- --- ------- ------ ----- ------ 97 * 0 Local GPCM 16 bit 256MB FLASH 98 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 99 * 100 */ 101 /* 102 * FLASH on the Local Bus 103 */ 104 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 105 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 106 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 107 #define CONFIG_SYS_FLASH_PROTECTION 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 110 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 111 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 112 113 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 114 BR_PS_16 | /* 16 bit port size */ \ 115 BR_MS_GPCM | /* MSEL = GPCM */ \ 116 BR_V) 117 118 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 119 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 120 OR_GPCM_SCY_5 | \ 121 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 122 123 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 124 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 126 127 /* 128 * PRIO1/PIGGY on the local bus CS1 129 */ 130 /* Window base at flash base */ 131 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 132 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 133 134 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 135 BR_PS_8 | /* 8 bit port size */ \ 136 BR_MS_GPCM | /* MSEL = GPCM */ \ 137 BR_V) 138 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 139 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 140 OR_GPCM_SCY_2 | \ 141 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 142 143 /* 144 * Serial Port 145 */ 146 #define CONFIG_CONS_INDEX 1 147 #define CONFIG_SYS_NS16550 148 #define CONFIG_SYS_NS16550_SERIAL 149 #define CONFIG_SYS_NS16550_REG_SIZE 1 150 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 151 152 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 153 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 154 155 /* Pass open firmware flat tree */ 156 #define CONFIG_OF_LIBFDT 157 #define CONFIG_OF_BOARD_SETUP 158 #define CONFIG_OF_STDOUT_VIA_ALIAS 159 160 /* 161 * QE UEC ethernet configuration 162 */ 163 #define CONFIG_UEC_ETH 164 #define CONFIG_ETHPRIME "UEC0" 165 166 #define CONFIG_UEC_ETH1 /* GETH1 */ 167 #define UEC_VERBOSE_DEBUG 1 168 169 #ifdef CONFIG_UEC_ETH1 170 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 171 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 172 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 173 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 174 #define CONFIG_SYS_UEC1_PHY_ADDR 0 175 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 176 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 177 #endif 178 179 /* 180 * Environment 181 */ 182 183 #ifndef CONFIG_SYS_RAMBOOT 184 #define CONFIG_ENV_IS_IN_FLASH 185 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 186 CONFIG_SYS_MONITOR_LEN) 187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 188 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 189 190 /* Address and size of Redundant Environment Sector */ 191 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 192 CONFIG_ENV_SECT_SIZE) 193 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 194 195 #else /* CFG_SYS_RAMBOOT */ 196 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 197 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 198 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 199 #define CONFIG_ENV_SIZE 0x2000 200 #endif /* CFG_SYS_RAMBOOT */ 201 202 /* I2C */ 203 #define CONFIG_HARD_I2C /* I2C with hardware support */ 204 #define CONFIG_FSL_I2C 205 #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ 206 #define CONFIG_SYS_I2C_SLAVE 0x7F 207 #define CONFIG_SYS_I2C_OFFSET 0x3000 208 209 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 210 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 211 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 212 #define CONFIG_SYS_DTT_MAX_TEMP 70 213 #define CONFIG_SYS_DTT_LOW_TEMP -30 214 #define CONFIG_SYS_DTT_HYSTERESIS 3 215 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) 216 217 #if defined(CONFIG_CMD_NAND) 218 #define CONFIG_NAND_KMETER1 219 #define CONFIG_SYS_MAX_NAND_DEVICE 1 220 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 221 #endif 222 223 #if defined(CONFIG_PCI) 224 #define CONFIG_CMD_PCI 225 #endif 226 227 /* 228 * For booting Linux, the board info and command line data 229 * have to be in the first 8 MB of memory, since this is 230 * the maximum mapped by the Linux kernel during initialization. 231 */ 232 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 233 234 /* 235 * Core HID Setup 236 */ 237 #define CONFIG_SYS_HID0_INIT 0x000000000 238 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 239 HID0_ENABLE_INSTRUCTION_CACHE) 240 #define CONFIG_SYS_HID2 HID2_HBE 241 242 /* 243 * MMU Setup 244 */ 245 246 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 247 248 /* DDR: cache cacheable */ 249 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 250 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 251 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 252 BATU_VS | BATU_VP) 253 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 254 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 255 256 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 257 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 258 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 259 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 260 | BATU_VP) 261 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 262 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 263 264 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 265 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 266 BATL_MEMCOHERENCE) 267 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 268 BATU_VS | BATU_VP) 269 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 270 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 271 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 272 273 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 274 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 275 BATL_MEMCOHERENCE) 276 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 277 BATU_VS | BATU_VP) 278 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 279 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 280 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 281 282 /* Stack in dcache: cacheable, no memory coherence */ 283 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 284 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 285 BATU_VS | BATU_VP) 286 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 287 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 288 289 /* 290 * Internal Definitions 291 */ 292 #define BOOTFLASH_START 0xF0000000 293 294 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 295 296 /* 297 * Environment Configuration 298 */ 299 #define CONFIG_ENV_OVERWRITE 300 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 301 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 302 #endif 303 304 #ifndef CONFIG_KM_DEF_ARCH 305 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 306 #endif 307 308 #define CONFIG_EXTRA_ENV_SETTINGS \ 309 CONFIG_KM_DEF_ENV \ 310 CONFIG_KM_DEF_ARCH \ 311 "dtt_bus=pca9547:70:a\0" \ 312 "EEprom_ivm=pca9547:70:9\0" \ 313 "newenv=" \ 314 "prot off 0xF00C0000 +0x40000 && " \ 315 "era 0xF00C0000 +0x40000\0" \ 316 "unlock=yes\0" \ 317 "" 318 319 #if defined(CONFIG_UEC_ETH) 320 #define CONFIG_HAS_ETH0 321 #endif 322 323 #endif /* __CONFIG_KM83XX_H */ 324