1 /* 2 * (C) Copyright 2003 3 * Texas Instruments. 4 * Kshitij Gupta <kshitij@ti.com> 5 * Configuation settings for the TI OMAP Innovator board. 6 * 7 * (C) Copyright 2004 8 * ARM Ltd. 9 * Philippe Robin, <philippe.robin@arm.com> 10 * Configuration for Integrator AP board. 11 *. 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CFG_MEMTEST_START 0x100000 38 #define CFG_MEMTEST_END 0x10000000 39 #define CFG_HZ 1000 40 #define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ 41 #define CFG_TIMERBASE 0x13000100 /* Timer1 */ 42 43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ 46 47 #undef CONFIG_INIT_CRITICAL 48 #define CONFIG_CM_INIT 1 49 #define CONFIG_CM_REMAP 1 50 #undef CONFIG_CM_SPD_DETECT 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) 56 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 57 58 /* 59 * PL010 Configuration 60 */ 61 #define CFG_PL010_SERIAL 62 #define CONFIG_CONS_INDEX 0 63 #define CONFIG_BAUDRATE 38400 64 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } 65 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 66 #define CFG_SERIAL0 0x16000000 67 #define CFG_SERIAL1 0x17000000 68 69 /*#define CONFIG_NET_MULTI */ 70 /*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ 71 72 73 /* 74 * Command line configuration. 75 */ 76 77 #define CONFIG_CMD_IMI 78 #define CONFIG_CMD_BDI 79 #define CONFIG_CMD_MEMORY 80 81 82 #define CONFIG_BOOTDELAY 2 83 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" 84 #define CONFIG_BOOTCOMMAND "" 85 86 /* 87 * Miscellaneous configurable options 88 */ 89 #define CFG_LONGHELP /* undef to save memory */ 90 #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ 91 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 92 /* Print Buffer Size */ 93 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 94 #define CFG_MAXARGS 16 /* max number of command args */ 95 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 96 97 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ 98 #define CFG_LOAD_ADDR 0x7fc0 /* default load address */ 99 100 /*----------------------------------------------------------------------- 101 * Stack sizes 102 * 103 * The stack sizes are set up in start.S using the settings below 104 */ 105 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 106 #ifdef CONFIG_USE_IRQ 107 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 108 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 109 #endif 110 111 /*----------------------------------------------------------------------- 112 * Physical Memory Map 113 */ 114 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 115 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 116 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 117 118 #define CFG_FLASH_BASE 0x24000000 119 120 /*----------------------------------------------------------------------- 121 * FLASH and environment organization 122 */ 123 #define CFG_ENV_IS_NOWHERE 124 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 125 #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ 126 /* timeout values are in ticks */ 127 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ 128 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ 129 #define CFG_MAX_FLASH_SECT 128 130 #define CFG_ENV_SIZE 32768 131 132 #define PHYS_FLASH_1 (CFG_FLASH_BASE) 133 134 /*----------------------------------------------------------------------- 135 * PCI definitions 136 */ 137 138 /*#define CONFIG_PCI /--* include pci support */ 139 #undef CONFIG_PCI_PNP 140 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 141 #define DEBUG 142 143 #define CONFIG_EEPRO100 144 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 145 146 147 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 148 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 149 150 /* PCI Base area */ 151 #define INTEGRATOR_PCI_BASE 0x40000000 152 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF 153 154 /* memory map as seen by the CPU on the local bus */ 155 #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ 156 #define CPU_PCI_IO_SIZE 0x10000 157 158 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ 159 #define CPU_PCI_CNFG_SIZE 0x1000000 160 161 #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ 162 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ 163 #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ 164 /* unused (128-16)M from B1000000-B7FFFFFF */ 165 #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ 166 /* unused ((128-16)M - 64K) from XXX */ 167 168 #define PCI_V3_BASE 0x62000000 169 170 /* V3 PCI bridge controller */ 171 #define V3_BASE 0x62000000 /* V360EPC registers */ 172 173 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) 174 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE) 175 176 177 #define V3_PCI_VENDOR 0x00000000 178 #define V3_PCI_DEVICE 0x00000002 179 #define V3_PCI_CMD 0x00000004 180 #define V3_PCI_STAT 0x00000006 181 #define V3_PCI_CC_REV 0x00000008 182 #define V3_PCI_HDR_CF 0x0000000C 183 #define V3_PCI_IO_BASE 0x00000010 184 #define V3_PCI_BASE0 0x00000014 185 #define V3_PCI_BASE1 0x00000018 186 #define V3_PCI_SUB_VENDOR 0x0000002C 187 #define V3_PCI_SUB_ID 0x0000002E 188 #define V3_PCI_ROM 0x00000030 189 #define V3_PCI_BPARAM 0x0000003C 190 #define V3_PCI_MAP0 0x00000040 191 #define V3_PCI_MAP1 0x00000044 192 #define V3_PCI_INT_STAT 0x00000048 193 #define V3_PCI_INT_CFG 0x0000004C 194 #define V3_LB_BASE0 0x00000054 195 #define V3_LB_BASE1 0x00000058 196 #define V3_LB_MAP0 0x0000005E 197 #define V3_LB_MAP1 0x00000062 198 #define V3_LB_BASE2 0x00000064 199 #define V3_LB_MAP2 0x00000066 200 #define V3_LB_SIZE 0x00000068 201 #define V3_LB_IO_BASE 0x0000006E 202 #define V3_FIFO_CFG 0x00000070 203 #define V3_FIFO_PRIORITY 0x00000072 204 #define V3_FIFO_STAT 0x00000074 205 #define V3_LB_ISTAT 0x00000076 206 #define V3_LB_IMASK 0x00000077 207 #define V3_SYSTEM 0x00000078 208 #define V3_LB_CFG 0x0000007A 209 #define V3_PCI_CFG 0x0000007C 210 #define V3_DMA_PCI_ADR0 0x00000080 211 #define V3_DMA_PCI_ADR1 0x00000090 212 #define V3_DMA_LOCAL_ADR0 0x00000084 213 #define V3_DMA_LOCAL_ADR1 0x00000094 214 #define V3_DMA_LENGTH0 0x00000088 215 #define V3_DMA_LENGTH1 0x00000098 216 #define V3_DMA_CSR0 0x0000008B 217 #define V3_DMA_CSR1 0x0000009B 218 #define V3_DMA_CTLB_ADR0 0x0000008C 219 #define V3_DMA_CTLB_ADR1 0x0000009C 220 #define V3_DMA_DELAY 0x000000E0 221 #define V3_MAIL_DATA 0x000000C0 222 #define V3_PCI_MAIL_IEWR 0x000000D0 223 #define V3_PCI_MAIL_IERD 0x000000D2 224 #define V3_LB_MAIL_IEWR 0x000000D4 225 #define V3_LB_MAIL_IERD 0x000000D6 226 #define V3_MAIL_WR_STAT 0x000000D8 227 #define V3_MAIL_RD_STAT 0x000000DA 228 #define V3_QBA_MAP 0x000000DC 229 230 /* SYSTEM register bits */ 231 #define V3_SYSTEM_M_RST_OUT (1 << 15) 232 #define V3_SYSTEM_M_LOCK (1 << 14) 233 234 /* PCI_CFG bits */ 235 #define V3_PCI_CFG_M_RETRY_EN (1 << 10) 236 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) 237 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) 238 239 /* PCI MAP register bits (PCI -> Local bus) */ 240 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 241 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) 242 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) 243 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) 244 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 245 #define V3_PCI_MAP_M_REG_EN (1 << 1) 246 #define V3_PCI_MAP_M_ENABLE (1 << 0) 247 248 /* 9 => 512M window size */ 249 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 250 251 /* A => 1024M window size */ 252 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 253 254 /* LB_BASE register bits (Local bus -> PCI) */ 255 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000 256 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) 257 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0 258 #define V3_LB_BASE_M_PREFETCH (1 << 3) 259 #define V3_LB_BASE_M_ENABLE (1 << 0) 260 261 /* PCI COMMAND REGISTER bits */ 262 #define V3_COMMAND_M_FBB_EN (1 << 9) 263 #define V3_COMMAND_M_SERR_EN (1 << 8) 264 #define V3_COMMAND_M_PAR_EN (1 << 6) 265 #define V3_COMMAND_M_MASTER_EN (1 << 2) 266 #define V3_COMMAND_M_MEM_EN (1 << 1) 267 #define V3_COMMAND_M_IO_EN (1 << 0) 268 269 #define INTEGRATOR_SC_BASE 0x11000000 270 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 271 #define INTEGRATOR_SC_PCIENABLE \ 272 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 273 274 /*----------------------------------------------------------------------- 275 * There are various dependencies on the core module (CM) fitted 276 * Users should refer to their CM user guide 277 * - when porting adjust u-boot/Makefile accordingly 278 * to define the necessary CONFIG_ s for the CM involved 279 * see e.g. integratorcp_CM926EJ-S_config 280 */ 281 #include "armcoremodule.h" 282 283 #endif /* __CONFIG_H */ 284