1*e62b008fSLinus Walleij /* 2*e62b008fSLinus Walleij * (C) Copyright 2012 3*e62b008fSLinus Walleij * Linaro 4*e62b008fSLinus Walleij * Linus Walleij <linus.walleij@linaro.org> 5*e62b008fSLinus Walleij * Common ARM Integrator configuration settings 6*e62b008fSLinus Walleij * 7*e62b008fSLinus Walleij * See file CREDITS for list of people who contributed to this 8*e62b008fSLinus Walleij * project. 9*e62b008fSLinus Walleij * 10*e62b008fSLinus Walleij * This program is free software; you can redistribute it and/or 11*e62b008fSLinus Walleij * modify it under the terms of the GNU General Public License as 12*e62b008fSLinus Walleij * published by the Free Software Foundation; either version 2 of 13*e62b008fSLinus Walleij * the License, or (at your option) any later version. 14*e62b008fSLinus Walleij * 15*e62b008fSLinus Walleij * This program is distributed in the hope that it will be useful, 16*e62b008fSLinus Walleij * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*e62b008fSLinus Walleij * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*e62b008fSLinus Walleij * GNU General Public License for more details. 19*e62b008fSLinus Walleij * 20*e62b008fSLinus Walleij * You should have received a copy of the GNU General Public License 21*e62b008fSLinus Walleij * along with this program; if not, write to the Free Software 22*e62b008fSLinus Walleij * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*e62b008fSLinus Walleij * MA 02111-1307 USA 24*e62b008fSLinus Walleij */ 25*e62b008fSLinus Walleij 26*e62b008fSLinus Walleij #define CONFIG_INTEGRATOR 27*e62b008fSLinus Walleij 28*e62b008fSLinus Walleij #define CONFIG_SYS_TEXT_BASE 0x01000000 29*e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_START 0x100000 30*e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_END 0x10000000 31*e62b008fSLinus Walleij #define CONFIG_SYS_HZ 1000 32*e62b008fSLinus Walleij #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ 33*e62b008fSLinus Walleij #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ 34*e62b008fSLinus Walleij #define CONFIG_SYS_LONGHELP 35*e62b008fSLinus Walleij #define CONFIG_SYS_HUSH_PARSER 36*e62b008fSLinus Walleij #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ 37*e62b008fSLinus Walleij #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 38*e62b008fSLinus Walleij #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 39*e62b008fSLinus Walleij #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ 40*e62b008fSLinus Walleij #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ 41*e62b008fSLinus Walleij 42*e62b008fSLinus Walleij #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43*e62b008fSLinus Walleij #define CONFIG_SETUP_MEMORY_TAGS 44*e62b008fSLinus Walleij #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ 45*e62b008fSLinus Walleij 46*e62b008fSLinus Walleij /* 47*e62b008fSLinus Walleij * There are various dependencies on the core module (CM) fitted 48*e62b008fSLinus Walleij * Users should refer to their CM user guide 49*e62b008fSLinus Walleij */ 50*e62b008fSLinus Walleij #include "armcoremodule.h" 51*e62b008fSLinus Walleij 52*e62b008fSLinus Walleij /* 53*e62b008fSLinus Walleij * Initialize and remap the core module, use SPD to detect memory size 54*e62b008fSLinus Walleij * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & 55*e62b008fSLinus Walleij * the core module has a CM_INIT register 56*e62b008fSLinus Walleij * then the U-Boot initialisation code will 57*e62b008fSLinus Walleij * e.g. ARM Boot Monitor or pre-loader is repeated once 58*e62b008fSLinus Walleij * (to re-initialise any existing CM_INIT settings to safe values). 59*e62b008fSLinus Walleij * 60*e62b008fSLinus Walleij * This is usually not the desired behaviour since the platform 61*e62b008fSLinus Walleij * will either reboot into the ARM monitor (or pre-loader) 62*e62b008fSLinus Walleij * or continuously cycle thru it without U-Boot running, 63*e62b008fSLinus Walleij * depending upon the setting of Integrator/CP switch S2-4. 64*e62b008fSLinus Walleij * 65*e62b008fSLinus Walleij * However it may be needed if Integrator/CP switch S2-1 66*e62b008fSLinus Walleij * is set OFF to boot direct into U-Boot. 67*e62b008fSLinus Walleij * In that case comment out the line below. 68*e62b008fSLinus Walleij */ 69*e62b008fSLinus Walleij #define CONFIG_CM_INIT 70*e62b008fSLinus Walleij #define CONFIG_CM_REMAP 71*e62b008fSLinus Walleij #define CONFIG_CM_SPD_DETECT 72*e62b008fSLinus Walleij 73*e62b008fSLinus Walleij /* 74*e62b008fSLinus Walleij * The ARM boot monitor initializes the board. 75*e62b008fSLinus Walleij * However, the default U-Boot code also performs the initialization. 76*e62b008fSLinus Walleij * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT 77*e62b008fSLinus Walleij * - see documentation supplied with board for details of how to choose the 78*e62b008fSLinus Walleij * image to run at reset/power up 79*e62b008fSLinus Walleij * e.g. whether the ARM Boot Monitor runs before U-Boot 80*e62b008fSLinus Walleij */ 81*e62b008fSLinus Walleij /* #define CONFIG_SKIP_LOWLEVEL_INIT */ 82*e62b008fSLinus Walleij 83*e62b008fSLinus Walleij /* 84*e62b008fSLinus Walleij * The ARM boot monitor does not relocate U-Boot. 85*e62b008fSLinus Walleij * However, the default U-Boot code performs the relocation check, 86*e62b008fSLinus Walleij * and may relocate the code if the memory map is changed. 87*e62b008fSLinus Walleij * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT 88*e62b008fSLinus Walleij */ 89*e62b008fSLinus Walleij /* #define SKIP_CONFIG_RELOCATE_UBOOT */ 90*e62b008fSLinus Walleij 91*e62b008fSLinus Walleij 92*e62b008fSLinus Walleij /* 93*e62b008fSLinus Walleij * Physical Memory Map 94*e62b008fSLinus Walleij */ 95*e62b008fSLinus Walleij #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 96*e62b008fSLinus Walleij #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 97*e62b008fSLinus Walleij #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 98*e62b008fSLinus Walleij #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 99*e62b008fSLinus Walleij #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE 100*e62b008fSLinus Walleij #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ 101*e62b008fSLinus Walleij CONFIG_SYS_INIT_RAM_SIZE - \ 102*e62b008fSLinus Walleij GENERATED_GBL_DATA_SIZE) 103*e62b008fSLinus Walleij #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET 104