188c307d1STim Harvey /* 288c307d1STim Harvey * Copyright (C) 2014 Gateworks Corporation 388c307d1STim Harvey * Author: Tim Harvey <tharvey@gateworks.com> 488c307d1STim Harvey * 588c307d1STim Harvey * SPDX-License-Identifier: GPL-2.0+ 688c307d1STim Harvey */ 788c307d1STim Harvey #ifndef __IMX6_SPL_CONFIG_H 888c307d1STim Harvey #define __IMX6_SPL_CONFIG_H 988c307d1STim Harvey 1088c307d1STim Harvey #ifdef CONFIG_SPL 1188c307d1STim Harvey 1288c307d1STim Harvey #define CONFIG_SPL_FRAMEWORK 1388c307d1STim Harvey 1488c307d1STim Harvey /* 1588c307d1STim Harvey * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: 1688c307d1STim Harvey * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF 1788c307d1STim Harvey * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well 1888c307d1STim Harvey * - BOOT ROM stack is at 0x0091FFB8 1988c307d1STim Harvey * - if icache/dcache is enabled (eFuse/strapping controlled) then the 2088c307d1STim Harvey * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to 2188c307d1STim Harvey * fit between 0x00907000 and 0x00918000. 2288c307d1STim Harvey * - Additionally the BOOT ROM loads what they consider the firmware image 2388c307d1STim Harvey * which consists of a 4K header in front of us that contains the IVT, DCD 2488c307d1STim Harvey * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 2588c307d1STim Harvey * or 64KB 2688c307d1STim Harvey */ 270351ef97SMarek Vasut #define CONFIG_SYS_THUMB_BUILD 28983e3700STom Rini #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 2988c307d1STim Harvey #define CONFIG_SPL_TEXT_BASE 0x00908000 30f91c09acSMarek Vasut #define CONFIG_SPL_MAX_SIZE 0x10000 3188c307d1STim Harvey #define CONFIG_SPL_STACK 0x0091FFB8 32*0405092bSStefan Agner /* 33*0405092bSStefan Agner * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the 34*0405092bSStefan Agner * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a 35*0405092bSStefan Agner * boot media (given that boot media specific offset is configured properly). 36*0405092bSStefan Agner */ 37*0405092bSStefan Agner #define CONFIG_SPL_PAD_TO 0x11000 3888c307d1STim Harvey 3988c307d1STim Harvey /* NAND support */ 4088c307d1STim Harvey #if defined(CONFIG_SPL_NAND_SUPPORT) 4188c307d1STim Harvey #define CONFIG_SPL_NAND_MXS 4288c307d1STim Harvey #endif 4388c307d1STim Harvey 4488c307d1STim Harvey /* MMC support */ 4588c307d1STim Harvey #if defined(CONFIG_SPL_MMC_SUPPORT) 46e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 47693d4c9fSSemen Protsenko #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ 4829100089SMarek Vasut #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 4988c307d1STim Harvey #endif 5088c307d1STim Harvey 5188c307d1STim Harvey /* SATA support */ 5288c307d1STim Harvey #if defined(CONFIG_SPL_SATA_SUPPORT) 5388c307d1STim Harvey #define CONFIG_SPL_SATA_BOOT_DEVICE 0 5488c307d1STim Harvey #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 5529100089SMarek Vasut #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 5688c307d1STim Harvey #endif 5788c307d1STim Harvey 5888c307d1STim Harvey /* Define the payload for FAT/EXT support */ 5988c307d1STim Harvey #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 60205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 6188c307d1STim Harvey #endif 6288c307d1STim Harvey 63e7d3b21bSPeng Fan #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL) 64f9e89ffdSPeng Fan #define CONFIG_SPL_BSS_START_ADDR 0x88200000 65f9e89ffdSPeng Fan #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 66f9e89ffdSPeng Fan #define CONFIG_SYS_SPL_MALLOC_START 0x88300000 67fef438d7SMarek Vasut #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 68f9e89ffdSPeng Fan #define CONFIG_SYS_TEXT_BASE 0x87800000 69f9e89ffdSPeng Fan #else 7088c307d1STim Harvey #define CONFIG_SPL_BSS_START_ADDR 0x18200000 7188c307d1STim Harvey #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 7288c307d1STim Harvey #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 73fef438d7SMarek Vasut #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 7488c307d1STim Harvey #define CONFIG_SYS_TEXT_BASE 0x17800000 7588c307d1STim Harvey #endif 76f9e89ffdSPeng Fan #endif 7788c307d1STim Harvey 7888c307d1STim Harvey #endif 79