xref: /rk3399_rockchip-uboot/include/configs/imx31_phycore.h (revision f4ea9f86d155aa7845f151c7a37699cdc3e4db2b)
1 /*
2  * (C) Copyright 2004
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Kshitij Gupta <kshitij@ti.com>
6  *
7  * Configuration settings for the phyCORE-i.MX31 board.
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30 
31 #include <asm/arch/imx-regs.h>
32 
33 /* High Level Configuration Options */
34 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
35 #define CONFIG_MX31			/* in a mx31 */
36 #define CONFIG_MX31_CLK32	32000
37 
38 #define CONFIG_DISPLAY_CPUINFO
39 #define CONFIG_DISPLAY_BOARDINFO
40 
41 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
44 
45 /*
46  * Size of malloc() pool
47  */
48 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
49 
50 /*
51  * Hardware drivers
52  */
53 
54 #define CONFIG_HARD_I2C
55 #define CONFIG_I2C_MXC
56 #define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
57 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
58 #define CONFIG_SYS_I2C_SPEED		100000
59 
60 #define CONFIG_MXC_UART
61 #define CONFIG_MXC_UART_BASE		UART1_BASE
62 
63 /* allow to overwrite serial and ethaddr */
64 #define CONFIG_ENV_OVERWRITE
65 #define CONFIG_CONS_INDEX	1
66 #define CONFIG_BAUDRATE		115200
67 
68 /***********************************************************
69  * Command definition
70  ***********************************************************/
71 
72 #include <config_cmd_default.h>
73 
74 #define CONFIG_CMD_PING
75 #define CONFIG_CMD_EEPROM
76 #define CONFIG_CMD_I2C
77 
78 #define CONFIG_BOOTDELAY	3
79 
80 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
81 					"1536k(kernel),-(root)"
82 
83 #define CONFIG_NETMASK		255.255.255.0
84 #define CONFIG_IPADDR		192.168.23.168
85 #define CONFIG_SERVERIP		192.168.23.2
86 
87 #define	CONFIG_EXTRA_ENV_SETTINGS					\
88 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
89 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
90 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
91 	"bootargs_flash=setenv bootargs $(bootargs) "			\
92 		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
93 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
94 	"bootcmd=run bootcmd_net\0"					\
95 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
96 		"tftpboot 0x80000000 $(uimage);bootm\0"			\
97 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
98 		"bootm 0x80000000\0"					\
99 	"unlock=yes\0"							\
100 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
101 	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
102 		"protect off 0xa0000000 +0x20000;"			\
103 		"erase 0xa0000000 +0x20000;"				\
104 		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
105 	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
106 		"erase 0xa0040000 +0x180000;"				\
107 		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
108 	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
109 		"erase 0xa01c0000 0xa1ffffff;"				\
110 		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
111 	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
112 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
113 		"sync:1241513985,vmode:0\0"
114 
115 
116 #define CONFIG_SMC911X
117 #define CONFIG_SMC911X_BASE	0xa8000000
118 #define CONFIG_SMC911X_32_BIT
119 
120 /*
121  * Miscellaneous configurable options
122  */
123 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
124 #define CONFIG_SYS_PROMPT		"uboot> "
125 /* Console I/O Buffer Size */
126 #define CONFIG_SYS_CBSIZE		256
127 /* Print Buffer Size */
128 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
129 					 sizeof(CONFIG_SYS_PROMPT) + 16)
130 /* max number of command args */
131 #define CONFIG_SYS_MAXARGS		16
132 /* Boot Argument Buffer Size */
133 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
134 
135 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
136 #define CONFIG_SYS_MEMTEST_END		0x10000
137 
138 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
139 
140 #define CONFIG_SYS_HZ			1000
141 
142 #define CONFIG_CMDLINE_EDITING
143 
144 /*
145  * Physical Memory Map
146  */
147 #define CONFIG_NR_DRAM_BANKS		1
148 #define PHYS_SDRAM_1			0x80000000
149 #define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
150 #define CONFIG_BOARD_EARLY_INIT_F
151 #define CONFIG_SYS_TEXT_BASE		0xA0000000
152 
153 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
154 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
155 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
156 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
157 						GENERATED_GBL_DATA_SIZE)
158 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
159 						CONFIG_SYS_GBL_DATA_OFFSET)
160 
161 /*
162  * FLASH and environment organization
163  */
164 #define CONFIG_SYS_FLASH_BASE		0xa0000000
165 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
166 #define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
167 /* Monitor at beginning of flash */
168 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
169 
170 #define CONFIG_ENV_IS_IN_EEPROM
171 #define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
172 #define CONFIG_ENV_SIZE				4096
173 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
177 
178 /*
179  * CFI FLASH driver setup
180  */
181 #define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
182 #define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
184 #define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
185 
186 /*
187  * Timeout for Flash Erase and Flash Write
188  * timeout values are in ticks
189  */
190 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
191 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
192 
193 /*
194  * JFFS2 partitions
195  */
196 #undef CONFIG_CMD_MTDPARTS
197 #define CONFIG_JFFS2_DEV	"nor0"
198 
199 /* EET platform additions */
200 #ifdef CONFIG_IMX31_PHYCORE_EET
201 #define CONFIG_BOARD_LATE_INIT
202 
203 #define CONFIG_MXC_GPIO
204 
205 #define CONFIG_HARD_SPI
206 #define CONFIG_MXC_SPI
207 #define CONFIG_CMD_SPI
208 
209 #define CONFIG_S6E63D6
210 
211 #define CONFIG_VIDEO
212 #define CONFIG_CFB_CONSOLE
213 #define CONFIG_VIDEO_MX3
214 #define CONFIG_VIDEO_LOGO
215 #define CONFIG_VIDEO_SW_CURSOR
216 #define CONFIG_VGA_AS_SINGLE_DEVICE
217 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
218 #define CONFIG_SPLASH_SCREEN
219 #define CONFIG_CMD_BMP
220 #define CONFIG_BMP_16BPP
221 #endif
222 
223 #endif /* __CONFIG_H */
224