xref: /rk3399_rockchip-uboot/include/configs/imx31_phycore.h (revision b8b71ffbc35fde6905e65ffdbf4e4b87efc26b7e)
1 /*
2  * (C) Copyright 2004
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Kshitij Gupta <kshitij@ti.com>
6  *
7  * Configuration settings for the phyCORE-i.MX31 board.
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30 
31  /* High Level Configuration Options */
32 #define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
33 #define CONFIG_MX31		1    /* in a mx31 */
34 #define CONFIG_MX31_HCLK_FREQ	26000000
35 #define CONFIG_MX31_CLK32	32000
36 
37 #define CONFIG_DISPLAY_CPUINFO
38 #define CONFIG_DISPLAY_BOARDINFO
39 
40 /* Temporarily disabled */
41 #if 0
42 #define CONFIG_OF_LIBFDT		1
43 #define CONFIG_FIT			1
44 #define CONFIG_FIT_VERBOSE		1
45 #endif
46 
47 #define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
48 #define CONFIG_SETUP_MEMORY_TAGS	1
49 #define CONFIG_INITRD_TAG		1
50 
51 /*
52  * Size of malloc() pool
53  */
54 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
55 #define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
56 
57 /*
58  * Hardware drivers
59  */
60 
61 #define CONFIG_HARD_I2C		1
62 #define CONFIG_I2C_MXC		1
63 #define CONFIG_SYS_I2C_MX31_PORT2	1
64 #define CONFIG_SYS_I2C_SPEED		100000
65 #define CONFIG_SYS_I2C_SLAVE		0xfe
66 
67 #define CONFIG_MXC_UART	1
68 #define CONFIG_SYS_MX31_UART1		1
69 
70 /* allow to overwrite serial and ethaddr */
71 #define CONFIG_ENV_OVERWRITE
72 #define CONFIG_CONS_INDEX	1
73 #define CONFIG_BAUDRATE		115200
74 #define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
75 
76 /***********************************************************
77  * Command definition
78  ***********************************************************/
79 
80 #include <config_cmd_default.h>
81 
82 #define CONFIG_CMD_PING
83 #define CONFIG_CMD_EEPROM
84 #define CONFIG_CMD_I2C
85 
86 #define CONFIG_BOOTDELAY	3
87 
88 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
89 
90 #define CONFIG_NETMASK		255.255.255.0
91 #define CONFIG_IPADDR		192.168.23.168
92 #define CONFIG_SERVERIP		192.168.23.2
93 
94 #define	CONFIG_EXTRA_ENV_SETTINGS											\
95 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"							\
96 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
97 	"bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2"				\
98 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)"								\
99 	"bootcmd=run bootcmd_net\0"											\
100 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 $(uimage); bootm\0"		\
101 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x80000000\0"				\
102 	"unlock=yes\0"													\
103 	"mtdparts=" MTDPARTS_DEFAULT "\0"										\
104 	"prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \
105 	"prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0"	\
106 	"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
107 
108 
109 #define CONFIG_DRIVER_SMC911X		1
110 #define CONFIG_DRIVER_SMC911X_BASE	0xa8000000
111 #define CONFIG_DRIVER_SMC911X_32_BIT	1
112 
113 /*
114  * Miscellaneous configurable options
115  */
116 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
117 #define CONFIG_SYS_PROMPT		"uboot> "
118 #define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
119 /* Print Buffer Size */
120 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
121 #define CONFIG_SYS_MAXARGS		16          /* max number of command args */
122 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
123 
124 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
125 #define CONFIG_SYS_MEMTEST_END		0x10000
126 
127 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
128 
129 #define CONFIG_SYS_HZ			1000
130 
131 #define CONFIG_CMDLINE_EDITING	1
132 
133 /*-----------------------------------------------------------------------
134  * Stack sizes
135  *
136  * The stack sizes are set up in start.S using the settings below
137  */
138 #define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */
139 
140 /*-----------------------------------------------------------------------
141  * Physical Memory Map
142  */
143 #define CONFIG_NR_DRAM_BANKS	1
144 #define PHYS_SDRAM_1		0x80000000
145 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
146 
147 /*-----------------------------------------------------------------------
148  * FLASH and environment organization
149  */
150 #define CONFIG_SYS_FLASH_BASE		0xa0000000
151 #define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT	259	     /* max number of sectors on one chip */
153 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
154 
155 #define	CONFIG_ENV_IS_IN_EEPROM		1
156 #define CONFIG_ENV_OFFSET			0x00	/* environment starts here     */
157 #define CONFIG_ENV_SIZE			4096
158 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets          */
160 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start      */
161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* length of byte address      */
162 
163 /*-----------------------------------------------------------------------
164  * CFI FLASH driver setup
165  */
166 #define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
167 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
168 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
169 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
170 
171 /* timeout values are in ticks */
172 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
174 
175 /*
176  * JFFS2 partitions
177  */
178 #undef CONFIG_CMD_MTDPARTS
179 #define CONFIG_JFFS2_DEV	"nor0"
180 
181 /* EET platform additions */
182 #ifdef CONFIG_IMX31_PHYCORE_EET
183 #define BOARD_LATE_INIT
184 
185 #define CONFIG_MX31_GPIO			1
186 
187 #define CONFIG_HARD_SPI				1
188 #define CONFIG_MXC_SPI				1
189 #define CONFIG_CMD_SPI
190 
191 #define CONFIG_S6E63D6				1
192 
193 #define CONFIG_LCD				1
194 #define CONFIG_VIDEO_MX3			1
195 #define CONFIG_SYS_WHITE_ON_BLACK		1
196 #define LCD_BPP					LCD_COLOR8
197 #define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
198 #define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
199 
200 #define	CONFIG_SPLASH_SCREEN			1
201 #define CONFIG_CMD_BMP				1
202 #endif
203 
204 #endif /* __CONFIG_H */
205