xref: /rk3399_rockchip-uboot/include/configs/imx31_phycore.h (revision 1fd92db83d399ff7918e51ba84bc73d2466b5eb6)
1 /*
2  * (C) Copyright 2004
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Kshitij Gupta <kshitij@ti.com>
6  *
7  * Configuration settings for the phyCORE-i.MX31 board.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 #include <asm/arch/imx-regs.h>
16 
17 /* High Level Configuration Options */
18 #define CONFIG_MX31			/* This is a mx31 */
19 #define CONFIG_MX31_CLK32	32000
20 
21 #define CONFIG_SYS_GENERIC_BOARD
22 
23 #define CONFIG_DISPLAY_CPUINFO
24 #define CONFIG_DISPLAY_BOARDINFO
25 
26 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
27 #define CONFIG_SETUP_MEMORY_TAGS
28 #define CONFIG_INITRD_TAG
29 
30 /*
31  * Size of malloc() pool
32  */
33 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
34 
35 /*
36  * Hardware drivers
37  */
38 
39 #define CONFIG_SYS_I2C
40 #define CONFIG_SYS_I2C_MXC
41 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
42 
43 #define CONFIG_MXC_UART
44 #define CONFIG_MXC_UART_BASE		UART1_BASE
45 
46 /* allow to overwrite serial and ethaddr */
47 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_CONS_INDEX	1
49 #define CONFIG_BAUDRATE		115200
50 
51 /***********************************************************
52  * Command definition
53  ***********************************************************/
54 
55 #include <config_cmd_default.h>
56 
57 #define CONFIG_CMD_PING
58 #define CONFIG_CMD_EEPROM
59 #define CONFIG_CMD_I2C
60 
61 #define CONFIG_BOOTDELAY	3
62 
63 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
64 					"1536k(kernel),-(root)"
65 
66 #define CONFIG_NETMASK		255.255.255.0
67 #define CONFIG_IPADDR		192.168.23.168
68 #define CONFIG_SERVERIP		192.168.23.2
69 
70 #define	CONFIG_EXTRA_ENV_SETTINGS					\
71 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
72 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
73 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
74 	"bootargs_flash=setenv bootargs $(bootargs) "			\
75 		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
76 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
77 	"bootcmd=run bootcmd_net\0"					\
78 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
79 		"tftpboot 0x80000000 $(uimage);bootm\0"			\
80 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
81 		"bootm 0x80000000\0"					\
82 	"unlock=yes\0"							\
83 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
84 	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
85 		"protect off 0xa0000000 +0x20000;"			\
86 		"erase 0xa0000000 +0x20000;"				\
87 		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
88 	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
89 		"erase 0xa0040000 +0x180000;"				\
90 		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
91 	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
92 		"erase 0xa01c0000 0xa1ffffff;"				\
93 		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
94 	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
95 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
96 		"sync:1241513985,vmode:0\0"
97 
98 
99 #define CONFIG_SMC911X
100 #define CONFIG_SMC911X_BASE	0xa8000000
101 #define CONFIG_SMC911X_32_BIT
102 
103 /*
104  * Miscellaneous configurable options
105  */
106 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
107 #define CONFIG_SYS_PROMPT		"uboot> "
108 /* Console I/O Buffer Size */
109 #define CONFIG_SYS_CBSIZE		256
110 /* Print Buffer Size */
111 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
112 					 sizeof(CONFIG_SYS_PROMPT) + 16)
113 /* max number of command args */
114 #define CONFIG_SYS_MAXARGS		16
115 /* Boot Argument Buffer Size */
116 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
117 
118 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
119 #define CONFIG_SYS_MEMTEST_END		0x10000
120 
121 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
122 
123 #define CONFIG_CMDLINE_EDITING
124 
125 /*
126  * Physical Memory Map
127  */
128 #define CONFIG_NR_DRAM_BANKS		1
129 #define PHYS_SDRAM_1			0x80000000
130 #define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
131 #define CONFIG_BOARD_EARLY_INIT_F
132 #define CONFIG_SYS_TEXT_BASE		0xA0000000
133 
134 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
135 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
136 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
137 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
138 						GENERATED_GBL_DATA_SIZE)
139 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
140 						CONFIG_SYS_GBL_DATA_OFFSET)
141 
142 /*
143  * FLASH and environment organization
144  */
145 #define CONFIG_SYS_FLASH_BASE		0xa0000000
146 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
148 /* Monitor at beginning of flash */
149 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
150 
151 #define CONFIG_ENV_IS_IN_EEPROM
152 #define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
153 #define CONFIG_ENV_SIZE				4096
154 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
158 
159 /*
160  * CFI FLASH driver setup
161  */
162 #define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
163 #define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
164 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
165 #define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
166 
167 /*
168  * Timeout for Flash Erase and Flash Write
169  * timeout values are in ticks
170  */
171 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
172 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
173 
174 /*
175  * JFFS2 partitions
176  */
177 #undef CONFIG_CMD_MTDPARTS
178 #define CONFIG_JFFS2_DEV	"nor0"
179 
180 /* EET platform additions */
181 #ifdef CONFIG_IMX31_PHYCORE_EET
182 #define CONFIG_BOARD_LATE_INIT
183 
184 #define CONFIG_MXC_GPIO
185 
186 #define CONFIG_HARD_SPI
187 #define CONFIG_MXC_SPI
188 #define CONFIG_CMD_SPI
189 
190 #define CONFIG_S6E63D6
191 
192 #define CONFIG_VIDEO
193 #define CONFIG_CFB_CONSOLE
194 #define CONFIG_VIDEO_MX3
195 #define CONFIG_VIDEO_LOGO
196 #define CONFIG_VIDEO_SW_CURSOR
197 #define CONFIG_VGA_AS_SINGLE_DEVICE
198 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
199 #define CONFIG_SPLASH_SCREEN
200 #define CONFIG_CMD_BMP
201 #define CONFIG_BMP_16BPP
202 #endif
203 
204 #endif /* __CONFIG_H */
205