xref: /rk3399_rockchip-uboot/include/configs/imx31_phycore.h (revision 19a9747535c105fa458d0c9929e6785cf56d1292)
1 /*
2  * (C) Copyright 2004
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Kshitij Gupta <kshitij@ti.com>
6  *
7  * Configuration settings for the phyCORE-i.MX31 board.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 #include <asm/arch/imx-regs.h>
16 
17 /* High Level Configuration Options */
18 #define CONFIG_MX31			/* This is a mx31 */
19 #define CONFIG_MX31_CLK32	32000
20 
21 #define CONFIG_DISPLAY_BOARDINFO
22 
23 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
24 #define CONFIG_SETUP_MEMORY_TAGS
25 #define CONFIG_INITRD_TAG
26 
27 /*
28  * Size of malloc() pool
29  */
30 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
31 
32 /*
33  * Hardware drivers
34  */
35 
36 #define CONFIG_SYS_I2C
37 #define CONFIG_SYS_I2C_MXC
38 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
39 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
40 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
41 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
42 
43 #define CONFIG_MXC_UART
44 #define CONFIG_MXC_UART_BASE		UART1_BASE
45 
46 /* allow to overwrite serial and ethaddr */
47 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_CONS_INDEX	1
49 #define CONFIG_BAUDRATE		115200
50 
51 /***********************************************************
52  * Command definition
53  ***********************************************************/
54 #define CONFIG_CMD_EEPROM
55 
56 
57 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
58 					"1536k(kernel),-(root)"
59 
60 #define CONFIG_NETMASK		255.255.255.0
61 #define CONFIG_IPADDR		192.168.23.168
62 #define CONFIG_SERVERIP		192.168.23.2
63 
64 #define	CONFIG_EXTRA_ENV_SETTINGS					\
65 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
66 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
67 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
68 	"bootargs_flash=setenv bootargs $(bootargs) "			\
69 		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
70 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
71 	"bootcmd=run bootcmd_net\0"					\
72 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
73 		"tftpboot 0x80000000 $(uimage);bootm\0"			\
74 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
75 		"bootm 0x80000000\0"					\
76 	"unlock=yes\0"							\
77 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
78 	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
79 		"protect off 0xa0000000 +0x20000;"			\
80 		"erase 0xa0000000 +0x20000;"				\
81 		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
82 	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
83 		"erase 0xa0040000 +0x180000;"				\
84 		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
85 	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
86 		"erase 0xa01c0000 0xa1ffffff;"				\
87 		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
88 	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
89 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
90 		"sync:1241513985,vmode:0\0"
91 
92 #define CONFIG_SMC911X
93 #define CONFIG_SMC911X_BASE	0xa8000000
94 #define CONFIG_SMC911X_32_BIT
95 
96 /*
97  * Miscellaneous configurable options
98  */
99 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
100 /* Console I/O Buffer Size */
101 #define CONFIG_SYS_CBSIZE		256
102 /* Print Buffer Size */
103 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
104 					 sizeof(CONFIG_SYS_PROMPT) + 16)
105 /* max number of command args */
106 #define CONFIG_SYS_MAXARGS		16
107 /* Boot Argument Buffer Size */
108 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
109 
110 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
111 #define CONFIG_SYS_MEMTEST_END		0x10000
112 
113 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
114 
115 #define CONFIG_CMDLINE_EDITING
116 
117 /*
118  * Physical Memory Map
119  */
120 #define CONFIG_NR_DRAM_BANKS		1
121 #define PHYS_SDRAM_1			0x80000000
122 #define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
123 #define CONFIG_BOARD_EARLY_INIT_F
124 #define CONFIG_SYS_TEXT_BASE		0xA0000000
125 
126 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
127 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
128 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
129 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
130 						GENERATED_GBL_DATA_SIZE)
131 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
132 						CONFIG_SYS_GBL_DATA_OFFSET)
133 
134 /*
135  * FLASH and environment organization
136  */
137 #define CONFIG_SYS_FLASH_BASE		0xa0000000
138 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
139 #define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
140 /* Monitor at beginning of flash */
141 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
142 
143 #define CONFIG_ENV_IS_IN_EEPROM
144 #define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
145 #define CONFIG_ENV_SIZE				4096
146 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
150 
151 /*
152  * CFI FLASH driver setup
153  */
154 #define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
155 #define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
157 #define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
158 
159 /*
160  * Timeout for Flash Erase and Flash Write
161  * timeout values are in ticks
162  */
163 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
164 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
165 
166 /*
167  * JFFS2 partitions
168  */
169 #undef CONFIG_CMD_MTDPARTS
170 #define CONFIG_JFFS2_DEV	"nor0"
171 
172 /* EET platform additions */
173 #ifdef CONFIG_IMX31_PHYCORE_EET
174 #define CONFIG_BOARD_LATE_INIT
175 
176 #define CONFIG_MXC_GPIO
177 
178 #define CONFIG_HARD_SPI
179 #define CONFIG_MXC_SPI
180 
181 #define CONFIG_S6E63D6
182 
183 #define CONFIG_VIDEO
184 #define CONFIG_CFB_CONSOLE
185 #define CONFIG_VIDEO_MX3
186 #define CONFIG_VIDEO_LOGO
187 #define CONFIG_VIDEO_SW_CURSOR
188 #define CONFIG_VGA_AS_SINGLE_DEVICE
189 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
190 #define CONFIG_SPLASH_SCREEN
191 #define CONFIG_CMD_BMP
192 #define CONFIG_BMP_16BPP
193 #endif
194 
195 #endif /* __CONFIG_H */
196