xref: /rk3399_rockchip-uboot/include/configs/imx31_phycore.h (revision 0c331ebcc6843bb5e4e6727d1b4a13ef2284a5ab)
1 /*
2  * (C) Copyright 2004
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Kshitij Gupta <kshitij@ti.com>
6  *
7  * Configuration settings for the phyCORE-i.MX31 board.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 #include <asm/arch/imx-regs.h>
16 
17 /* High Level Configuration Options */
18 #define CONFIG_MX31			/* This is a mx31 */
19 #define CONFIG_MX31_CLK32	32000
20 
21 #define CONFIG_DISPLAY_CPUINFO
22 #define CONFIG_DISPLAY_BOARDINFO
23 
24 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
27 
28 /*
29  * Size of malloc() pool
30  */
31 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
32 
33 /*
34  * Hardware drivers
35  */
36 
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_MXC
39 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
40 
41 #define CONFIG_MXC_UART
42 #define CONFIG_MXC_UART_BASE		UART1_BASE
43 
44 /* allow to overwrite serial and ethaddr */
45 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_CONS_INDEX	1
47 #define CONFIG_BAUDRATE		115200
48 
49 /***********************************************************
50  * Command definition
51  ***********************************************************/
52 
53 #include <config_cmd_default.h>
54 
55 #define CONFIG_CMD_PING
56 #define CONFIG_CMD_EEPROM
57 #define CONFIG_CMD_I2C
58 
59 #define CONFIG_BOOTDELAY	3
60 
61 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
62 					"1536k(kernel),-(root)"
63 
64 #define CONFIG_NETMASK		255.255.255.0
65 #define CONFIG_IPADDR		192.168.23.168
66 #define CONFIG_SERVERIP		192.168.23.2
67 
68 #define	CONFIG_EXTRA_ENV_SETTINGS					\
69 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
70 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
71 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
72 	"bootargs_flash=setenv bootargs $(bootargs) "			\
73 		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
74 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
75 	"bootcmd=run bootcmd_net\0"					\
76 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
77 		"tftpboot 0x80000000 $(uimage);bootm\0"			\
78 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
79 		"bootm 0x80000000\0"					\
80 	"unlock=yes\0"							\
81 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
82 	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
83 		"protect off 0xa0000000 +0x20000;"			\
84 		"erase 0xa0000000 +0x20000;"				\
85 		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
86 	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
87 		"erase 0xa0040000 +0x180000;"				\
88 		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
89 	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
90 		"erase 0xa01c0000 0xa1ffffff;"				\
91 		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
92 	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
93 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
94 		"sync:1241513985,vmode:0\0"
95 
96 
97 #define CONFIG_SMC911X
98 #define CONFIG_SMC911X_BASE	0xa8000000
99 #define CONFIG_SMC911X_32_BIT
100 
101 /*
102  * Miscellaneous configurable options
103  */
104 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
105 #define CONFIG_SYS_PROMPT		"uboot> "
106 /* Console I/O Buffer Size */
107 #define CONFIG_SYS_CBSIZE		256
108 /* Print Buffer Size */
109 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
110 					 sizeof(CONFIG_SYS_PROMPT) + 16)
111 /* max number of command args */
112 #define CONFIG_SYS_MAXARGS		16
113 /* Boot Argument Buffer Size */
114 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
115 
116 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
117 #define CONFIG_SYS_MEMTEST_END		0x10000
118 
119 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
120 
121 #define CONFIG_CMDLINE_EDITING
122 
123 /*
124  * Physical Memory Map
125  */
126 #define CONFIG_NR_DRAM_BANKS		1
127 #define PHYS_SDRAM_1			0x80000000
128 #define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
129 #define CONFIG_BOARD_EARLY_INIT_F
130 #define CONFIG_SYS_TEXT_BASE		0xA0000000
131 
132 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
133 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
134 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
135 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
136 						GENERATED_GBL_DATA_SIZE)
137 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
138 						CONFIG_SYS_GBL_DATA_OFFSET)
139 
140 /*
141  * FLASH and environment organization
142  */
143 #define CONFIG_SYS_FLASH_BASE		0xa0000000
144 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
145 #define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
146 /* Monitor at beginning of flash */
147 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
148 
149 #define CONFIG_ENV_IS_IN_EEPROM
150 #define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
151 #define CONFIG_ENV_SIZE				4096
152 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
156 
157 /*
158  * CFI FLASH driver setup
159  */
160 #define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
161 #define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
162 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
163 #define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
164 
165 /*
166  * Timeout for Flash Erase and Flash Write
167  * timeout values are in ticks
168  */
169 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
170 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
171 
172 /*
173  * JFFS2 partitions
174  */
175 #undef CONFIG_CMD_MTDPARTS
176 #define CONFIG_JFFS2_DEV	"nor0"
177 
178 /* EET platform additions */
179 #ifdef CONFIG_IMX31_PHYCORE_EET
180 #define CONFIG_BOARD_LATE_INIT
181 
182 #define CONFIG_MXC_GPIO
183 
184 #define CONFIG_HARD_SPI
185 #define CONFIG_MXC_SPI
186 #define CONFIG_CMD_SPI
187 
188 #define CONFIG_S6E63D6
189 
190 #define CONFIG_VIDEO
191 #define CONFIG_CFB_CONSOLE
192 #define CONFIG_VIDEO_MX3
193 #define CONFIG_VIDEO_LOGO
194 #define CONFIG_VIDEO_SW_CURSOR
195 #define CONFIG_VGA_AS_SINGLE_DEVICE
196 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
197 #define CONFIG_SPLASH_SCREEN
198 #define CONFIG_CMD_BMP
199 #define CONFIG_BMP_16BPP
200 #endif
201 
202 #endif /* __CONFIG_H */
203