1*ebf2b9e3SZubair Lutfullah Kakakhel /* 2*ebf2b9e3SZubair Lutfullah Kakakhel * Copyright (C) 2016, Imagination Technologies Ltd. 3*ebf2b9e3SZubair Lutfullah Kakakhel * 4*ebf2b9e3SZubair Lutfullah Kakakhel * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 5*ebf2b9e3SZubair Lutfullah Kakakhel * 6*ebf2b9e3SZubair Lutfullah Kakakhel * SPDX-License-Identifier: GPL-2.0+ 7*ebf2b9e3SZubair Lutfullah Kakakhel * 8*ebf2b9e3SZubair Lutfullah Kakakhel * Imagination Technologies Ltd. MIPSfpga 9*ebf2b9e3SZubair Lutfullah Kakakhel */ 10*ebf2b9e3SZubair Lutfullah Kakakhel 11*ebf2b9e3SZubair Lutfullah Kakakhel #ifndef __XILFPGA_CONFIG_H 12*ebf2b9e3SZubair Lutfullah Kakakhel #define __XILFPGA_CONFIG_H 13*ebf2b9e3SZubair Lutfullah Kakakhel 14*ebf2b9e3SZubair Lutfullah Kakakhel /* BootROM + MIG is pretty smart. DDR and Cache initialized */ 15*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SKIP_LOWLEVEL_INIT 16*ebf2b9e3SZubair Lutfullah Kakakhel 17*ebf2b9e3SZubair Lutfullah Kakakhel /*-------------------------------------------- 18*ebf2b9e3SZubair Lutfullah Kakakhel * CPU configuration 19*ebf2b9e3SZubair Lutfullah Kakakhel */ 20*ebf2b9e3SZubair Lutfullah Kakakhel /* CPU Timer rate */ 21*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 22*ebf2b9e3SZubair Lutfullah Kakakhel 23*ebf2b9e3SZubair Lutfullah Kakakhel /* Cache Configuration */ 24*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT 25*ebf2b9e3SZubair Lutfullah Kakakhel 26*ebf2b9e3SZubair Lutfullah Kakakhel /*---------------------------------------------------------------------- 27*ebf2b9e3SZubair Lutfullah Kakakhel * Memory Layout 28*ebf2b9e3SZubair Lutfullah Kakakhel */ 29*ebf2b9e3SZubair Lutfullah Kakakhel 30*ebf2b9e3SZubair Lutfullah Kakakhel /* SDRAM Configuration (for final code, data, stack, heap) */ 31*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_SDRAM_BASE 0x80000000 32*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ 33*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_INIT_SP_ADDR \ 34*ebf2b9e3SZubair Lutfullah Kakakhel (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) 35*ebf2b9e3SZubair Lutfullah Kakakhel 36*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MALLOC_LEN (256 << 10) 37*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 38*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ 39*ebf2b9e3SZubair Lutfullah Kakakhel 40*ebf2b9e3SZubair Lutfullah Kakakhel /*---------------------------------------------------------------------- 41*ebf2b9e3SZubair Lutfullah Kakakhel * Commands 42*ebf2b9e3SZubair Lutfullah Kakakhel */ 43*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_LONGHELP /* undef to save memory */ 44*ebf2b9e3SZubair Lutfullah Kakakhel 45*ebf2b9e3SZubair Lutfullah Kakakhel /*------------------------------------------------------------ 46*ebf2b9e3SZubair Lutfullah Kakakhel * Console Configuration 47*ebf2b9e3SZubair Lutfullah Kakakhel */ 48*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 49*ebf2b9e3SZubair Lutfullah Kakakhel 50*ebf2b9e3SZubair Lutfullah Kakakhel /* ------------------------------------------------- 51*ebf2b9e3SZubair Lutfullah Kakakhel * Environment 52*ebf2b9e3SZubair Lutfullah Kakakhel */ 53*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_ENV_SIZE 0x4000 54*ebf2b9e3SZubair Lutfullah Kakakhel 55*ebf2b9e3SZubair Lutfullah Kakakhel /* --------------------------------------------------------------------- 56*ebf2b9e3SZubair Lutfullah Kakakhel * Board boot configuration 57*ebf2b9e3SZubair Lutfullah Kakakhel */ 58*ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 59*ebf2b9e3SZubair Lutfullah Kakakhel 60*ebf2b9e3SZubair Lutfullah Kakakhel #endif /* __XILFPGA_CONFIG_H */ 61