1 /* 2 * (C) Copyright 2013 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * Based on: 6 * Copyright (c) 2011 IDS GmbH, Germany 7 * Sergej Stepanov <ste@ids.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_MPC831x 19 #define CONFIG_MPC8313 20 #define CONFIG_IDS8313 21 22 #define CONFIG_FSL_ELBC 23 24 #define CONFIG_MISC_INIT_R 25 26 #define CONFIG_BOOT_RETRY_TIME 900 27 #define CONFIG_BOOT_RETRY_MIN 30 28 #define CONFIG_BOOTDELAY 1 29 #define CONFIG_RESET_TO_RETRY 30 31 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 32 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 33 34 #define CONFIG_SYS_IMMR 0xF0000000 35 36 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 37 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 38 39 /* 40 * Hardware Reset Configuration Word 41 * if CLKIN is 66.000MHz, then 42 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz 43 */ 44 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ 45 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 46 HRCWL_CSB_TO_CLKIN_2X1 |\ 47 HRCWL_CORE_TO_CSB_2X1) 48 49 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ 50 HRCWH_CORE_ENABLE |\ 51 HRCWH_FROM_0XFFF00100 |\ 52 HRCWH_BOOTSEQ_DISABLE |\ 53 HRCWH_SW_WATCHDOG_DISABLE |\ 54 HRCWH_ROM_LOC_LOCAL_8BIT |\ 55 HRCWH_RL_EXT_LEGACY |\ 56 HRCWH_TSEC1M_IN_MII |\ 57 HRCWH_TSEC2M_IN_MII |\ 58 HRCWH_BIG_ENDIAN) 59 60 #define CONFIG_SYS_SICRH 0x00000000 61 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) 62 63 #define CONFIG_HWCONFIG 64 65 #define CONFIG_SYS_HID0_INIT 0x000000000 66 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ 67 HID0_ENABLE_INSTRUCTION_CACHE |\ 68 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) 69 70 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) 71 72 /* 73 * Definitions for initial stack pointer and data area (in DCACHE ) 74 */ 75 #define CONFIG_SYS_INIT_RAM_LOCK 76 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 77 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ 78 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 79 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 80 - CONFIG_SYS_GBL_DATA_SIZE) 81 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 82 83 /* 84 * Local Bus LCRR and LBCR regs 85 */ 86 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 87 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 88 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ 89 (0xFF << LBCR_BMT_SHIFT) |\ 90 0xF) 91 92 #define CONFIG_SYS_LBC_MRTPR 0x20000000 93 94 /* 95 * Internal Definitions 96 */ 97 /* 98 * DDR Setup 99 */ 100 #define CONFIG_SYS_DDR_BASE 0x00000000 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 102 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 103 104 /* 105 * Manually set up DDR parameters, 106 * as this board has not the SPD connected to I2C. 107 */ 108 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 109 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ 110 0x00010000 |\ 111 CSCONFIG_ROW_BIT_13 |\ 112 CSCONFIG_COL_BIT_10) 113 114 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ 115 CSCONFIG_BANK_BIT_3) 116 117 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ 118 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ 119 (3 << TIMING_CFG0_WRT_SHIFT) |\ 120 (3 << TIMING_CFG0_RRT_SHIFT) |\ 121 (3 << TIMING_CFG0_WWT_SHIFT) |\ 122 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ 123 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ 124 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 125 (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 126 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ 127 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ 128 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ 129 (7 << TIMING_CFG1_CASLAT_SHIFT) |\ 130 (4 << TIMING_CFG1_REFREC_SHIFT) |\ 131 (4 << TIMING_CFG1_WRREC_SHIFT) |\ 132 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ 133 (2 << TIMING_CFG1_WRTORD_SHIFT)) 134 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ 135 (5 << TIMING_CFG2_CPO_SHIFT) |\ 136 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ 137 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ 138 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ 139 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ 140 (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 141 142 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ 143 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 144 145 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ 146 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ 147 SDRAM_CFG_DBW_32 |\ 148 SDRAM_CFG_SDRAM_TYPE_DDR2) 149 150 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 151 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ 152 (0x0242 << SDRAM_MODE_SD_SHIFT)) 153 #define CONFIG_SYS_DDR_MODE_2 0x00000000 154 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 155 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ 156 DDRCDR_PZ_NOMZ |\ 157 DDRCDR_NZ_NOMZ |\ 158 DDRCDR_ODT |\ 159 DDRCDR_M_ODR |\ 160 DDRCDR_Q_DRN) 161 162 /* 163 * on-board devices 164 */ 165 #define CONFIG_TSEC1 166 #define CONFIG_TSEC2 167 #define CONFIG_TSEC_ENET 168 #define CONFIG_HARD_SPI 169 #define CONFIG_HARD_I2C 170 171 /* 172 * NOR FLASH setup 173 */ 174 #define CONFIG_SYS_FLASH_CFI 175 #define CONFIG_FLASH_CFI_DRIVER 176 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 177 #define CONFIG_FLASH_SHOW_PROGRESS 50 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 179 180 #define CONFIG_SYS_FLASH_BASE 0xFF800000 181 #define CONFIG_SYS_FLASH_SIZE 8 182 #define CONFIG_SYS_FLASH_PROTECTION 183 184 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 185 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 186 187 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 188 BR_PS_8 |\ 189 BR_MS_GPCM |\ 190 BR_V) 191 192 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 193 OR_GPCM_SCY_10 |\ 194 OR_GPCM_EHTR |\ 195 OR_GPCM_TRLX |\ 196 OR_GPCM_CSNT |\ 197 OR_GPCM_EAD) 198 #define CONFIG_SYS_MAX_FLASH_BANKS 1 199 #define CONFIG_SYS_MAX_FLASH_SECT 128 200 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 203 204 /* 205 * NAND FLASH setup 206 */ 207 #define CONFIG_SYS_NAND_BASE 0xE1000000 208 #define CONFIG_SYS_MAX_NAND_DEVICE 1 209 #define CONFIG_SYS_NAND_MAX_CHIPS 1 210 #define CONFIG_NAND_FSL_ELBC 211 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) 212 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 213 #define NAND_CACHE_PAGES 64 214 215 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 216 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 217 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 218 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 219 220 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ 221 (2<<BR_DECC_SHIFT) |\ 222 BR_PS_8 |\ 223 BR_MS_FCM |\ 224 BR_V) 225 226 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ 227 OR_FCM_PGS |\ 228 OR_FCM_CSCT |\ 229 OR_FCM_CST |\ 230 OR_FCM_CHT |\ 231 OR_FCM_SCY_4 |\ 232 OR_FCM_TRLX |\ 233 OR_FCM_EHTR |\ 234 OR_FCM_RST) 235 236 /* 237 * MRAM setup 238 */ 239 #define CONFIG_SYS_MRAM_BASE 0xE2000000 240 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ 241 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE 242 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ 243 244 #define CONFIG_SYS_OR_TIMING_MRAM 245 246 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ 247 BR_PS_8 |\ 248 BR_MS_GPCM |\ 249 BR_V) 250 251 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 252 253 /* 254 * CPLD setup 255 */ 256 #define CONFIG_SYS_CPLD_BASE 0xE3000000 257 #define CONFIG_SYS_CPLD_SIZE 0x8000 258 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE 259 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E 260 261 #define CONFIG_SYS_OR_TIMING_MRAM 262 263 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ 264 BR_PS_8 |\ 265 BR_MS_GPCM |\ 266 BR_V) 267 268 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 269 270 /* 271 * HW-Watchdog 272 */ 273 #define CONFIG_WATCHDOG 1 274 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF 275 276 /* 277 * I2C setup 278 */ 279 #define CONFIG_SYS_I2C 280 #define CONFIG_SYS_I2C_FSL 281 #define CONFIG_SYS_FSL_I2C_SPEED 400000 282 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 283 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 284 #define CONFIG_RTC_PCF8563 285 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 286 287 /* 288 * SPI setup 289 */ 290 #ifdef CONFIG_HARD_SPI 291 #define CONFIG_MPC8XXX_SPI 292 #define CONFIG_SYS_GPIO1_PRELIM 293 #define CONFIG_SYS_GPIO1_DIR 0x00000001 294 #define CONFIG_SYS_GPIO1_DAT 0x00000001 295 #endif 296 297 /* 298 * Ethernet setup 299 */ 300 #ifdef CONFIG_TSEC1 301 #define CONFIG_HAS_ETH0 302 #define CONFIG_TSEC1_NAME "TSEC0" 303 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 304 #define TSEC1_PHY_ADDR 0x1 305 #define TSEC1_FLAGS TSEC_GIGABIT 306 #define TSEC1_PHYIDX 0 307 #endif 308 309 #ifdef CONFIG_TSEC2 310 #define CONFIG_HAS_ETH1 311 #define CONFIG_TSEC2_NAME "TSEC1" 312 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 313 #define TSEC2_PHY_ADDR 0x3 314 #define TSEC2_FLAGS TSEC_GIGABIT 315 #define TSEC2_PHYIDX 0 316 #endif 317 #define CONFIG_ETHPRIME "TSEC1" 318 319 /* 320 * Serial Port 321 */ 322 #define CONFIG_CONS_INDEX 1 323 #define CONFIG_SYS_NS16550_SERIAL 324 #define CONFIG_SYS_NS16550_REG_SIZE 1 325 326 #define CONFIG_SYS_BAUDRATE_TABLE \ 327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 330 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 331 332 #define CONFIG_HAS_FSL_DR_USB 333 #define CONFIG_SYS_SCCR_USBDRCM 3 334 335 /* 336 * BAT's 337 */ 338 #define CONFIG_HIGH_BATS 339 340 /* DDR @ 0x00000000 */ 341 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ 342 BATL_PP_10) 343 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ 344 BATU_BL_256M |\ 345 BATU_VS |\ 346 BATU_VP) 347 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 348 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 349 350 /* Initial RAM @ 0xFD000000 */ 351 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ 352 BATL_PP_10 |\ 353 BATL_GUARDEDSTORAGE) 354 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ 355 BATU_BL_256K |\ 356 BATU_VS |\ 357 BATU_VP) 358 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 359 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 360 361 /* FLASH @ 0xFF800000 */ 362 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ 363 BATL_PP_10 |\ 364 BATL_GUARDEDSTORAGE) 365 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ 366 BATU_BL_8M |\ 367 BATU_VS |\ 368 BATU_VP) 369 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ 370 BATL_PP_10 |\ 371 BATL_CACHEINHIBIT |\ 372 BATL_GUARDEDSTORAGE) 373 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 374 375 #define CONFIG_SYS_IBAT3L (0) 376 #define CONFIG_SYS_IBAT3U (0) 377 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 378 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 379 380 #define CONFIG_SYS_IBAT4L (0) 381 #define CONFIG_SYS_IBAT4U (0) 382 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 383 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 384 385 /* IMMRBAR @ 0xF0000000 */ 386 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ 387 BATL_PP_10 |\ 388 BATL_CACHEINHIBIT |\ 389 BATL_GUARDEDSTORAGE) 390 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ 391 BATU_BL_128M |\ 392 BATU_VS |\ 393 BATU_VP) 394 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 395 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 396 397 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ 398 #define CONFIG_SYS_IBAT6L (0xE0000000 |\ 399 BATL_PP_10 |\ 400 BATL_GUARDEDSTORAGE) 401 #define CONFIG_SYS_IBAT6U (0xE0000000 |\ 402 BATU_BL_256M |\ 403 BATU_VS |\ 404 BATU_VP) 405 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 406 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 407 408 #define CONFIG_SYS_IBAT7L (0) 409 #define CONFIG_SYS_IBAT7U (0) 410 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 411 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 412 413 /* 414 * U-Boot environment setup 415 */ 416 #define CONFIG_CMD_NAND 417 #define CONFIG_CMD_MII 418 #define CONFIG_CMD_DATE 419 #define CONFIG_CMDLINE_EDITING 420 #define CONFIG_CMD_JFFS2 421 #define CONFIG_BOOTP_SUBNETMASK 422 #define CONFIG_BOOTP_GATEWAY 423 #define CONFIG_BOOTP_HOSTNAME 424 #define CONFIG_BOOTP_BOOTPATH 425 #define CONFIG_BOOTP_BOOTFILESIZE 426 427 /* 428 * The reserved memory 429 */ 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 431 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 432 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) 433 434 /* 435 * Environment Configuration 436 */ 437 #define CONFIG_ENV_IS_IN_FLASH 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 439 + CONFIG_SYS_MONITOR_LEN) 440 #define CONFIG_ENV_SIZE 0x20000 441 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 442 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 443 444 #define CONFIG_NETDEV eth1 445 #define CONFIG_HOSTNAME ids8313 446 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" 447 #define CONFIG_BOOTFILE "ids8313/uImage" 448 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" 449 #define CONFIG_FDTFILE "ids8313/ids8313.dtb" 450 #define CONFIG_LOADADDR 0x400000 451 #define CONFIG_CMD_ENV_FLAGS 452 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" 453 454 #define CONFIG_BAUDRATE 115200 455 456 /* Initial Memory map for Linux*/ 457 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 #define CONFIG_SYS_LONGHELP 463 #define CONFIG_SYS_CBSIZE 1024 464 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 465 + sizeof(CONFIG_SYS_PROMPT)+16) 466 #define CONFIG_SYS_MAXARGS 16 467 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 468 469 #define CONFIG_SYS_MEMTEST_START 0x00001000 470 #define CONFIG_SYS_MEMTEST_END 0x00C00000 471 472 #define CONFIG_SYS_LOAD_ADDR 0x100000 473 #define CONFIG_MII 474 #define CONFIG_LOADS_ECHO 475 #define CONFIG_TIMESTAMP 476 #define CONFIG_PREBOOT "echo;" \ 477 "echo Type \\\"run nfsboot\\\" " \ 478 "to mount root filesystem over NFS;echo" 479 #undef CONFIG_BOOTARGS 480 #define CONFIG_BOOTCOMMAND "run boot_cramfs" 481 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 482 483 #define CONFIG_JFFS2_NAND 484 #define CONFIG_JFFS2_DEV "0" 485 486 /* mtdparts command line support */ 487 #define CONFIG_CMD_MTDPARTS 488 #define CONFIG_FLASH_CFI_MTD 489 #define CONFIG_MTD_DEVICE 490 #define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash" 491 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \ 492 "768k(BOOT-BIN)," \ 493 "128k(BOOT-ENV),128k(BOOT-REDENV);" \ 494 "e1000000.flash:-(ubi)" 495 496 #define CONFIG_EXTRA_ENV_SETTINGS \ 497 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 498 "ethprime=TSEC1\0" \ 499 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 500 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ 501 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 502 " +${filesize}; " \ 503 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 504 " +${filesize}; " \ 505 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 506 " ${filesize}; " \ 507 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 508 " +${filesize}; " \ 509 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 510 " ${filesize}\0" \ 511 "console=ttyS0\0" \ 512 "fdtaddr=0x780000\0" \ 513 "kernel_addr=ff800000\0" \ 514 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ 515 "setbootargs=setenv bootargs " \ 516 "root=${rootdev} rw console=${console}," \ 517 "${baudrate} ${othbootargs}\0" \ 518 "setipargs=setenv bootargs root=${rootdev} rw " \ 519 "nfsroot=${serverip}:${rootpath} " \ 520 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 521 "${netmask}:${hostname}:${netdev}:off " \ 522 "console=${console},${baudrate} ${othbootargs}\0" \ 523 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 524 "mtdids=" MTDIDS_DEFAULT "\0" \ 525 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 526 "\0" 527 528 #define CONFIG_NFSBOOTCOMMAND \ 529 "setenv rootdev /dev/nfs;" \ 530 "run setipargs;run addmtd;" \ 531 "tftp ${loadaddr} ${bootfile};" \ 532 "tftp ${fdtaddr} ${fdtfile};" \ 533 "fdt addr ${fdtaddr};" \ 534 "bootm ${loadaddr} - ${fdtaddr}" 535 536 /* UBI Support */ 537 #define CONFIG_CMD_NAND_TRIMFFS 538 #define CONFIG_CMD_UBI 539 #define CONFIG_CMD_UBIFS 540 #define CONFIG_RBTREE 541 #define CONFIG_LZO 542 #define CONFIG_MTD_PARTITIONS 543 544 /* bootcount support */ 545 #define CONFIG_BOOTCOUNT_LIMIT 546 #define CONFIG_BOOTCOUNT_I2C 547 #define CONFIG_BOOTCOUNT_ALEN 1 548 #define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 549 550 #define CONFIG_VERSION_VARIABLE 551 552 #define CONFIG_IMAGE_FORMAT_LEGACY 553 #define CONFIG_CMD_HASH 554 #define CONFIG_SHA1 555 #define CONFIG_SHA256 556 557 #endif /* __CONFIG_H */ 558