1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #ifdef CONFIG_HRCON_DH 24 #define CONFIG_IDENT_STRING " hrcon dh 0.01" 25 #else 26 #define CONFIG_IDENT_STRING " hrcon 0.01" 27 #endif 28 29 #define CONFIG_BOARD_EARLY_INIT_F 30 #define CONFIG_BOARD_EARLY_INIT_R 31 #define CONFIG_LAST_STAGE_INIT 32 33 #define CONFIG_MMC 34 #define CONFIG_FSL_ESDHC 35 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 36 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 37 38 #define CONFIG_CMD_MMC 39 #define CONFIG_GENERIC_MMC 40 #define CONFIG_DOS_PARTITION 41 #define CONFIG_CMD_EXT2 42 43 #define CONFIG_CMD_FPGAD 44 #define CONFIG_CMD_IOLOOP 45 46 /* 47 * System Clock Setup 48 */ 49 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 50 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 51 52 /* 53 * Hardware Reset Configuration Word 54 * if CLKIN is 66.66MHz, then 55 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 56 * We choose the A type silicon as default, so the core is 400Mhz. 57 */ 58 #define CONFIG_SYS_HRCW_LOW (\ 59 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 60 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 61 HRCWL_SVCOD_DIV_2 |\ 62 HRCWL_CSB_TO_CLKIN_4X1 |\ 63 HRCWL_CORE_TO_CSB_3X1) 64 /* 65 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 66 * in 8308's HRCWH according to the manual, but original Freescale's 67 * code has them and I've expirienced some problems using the board 68 * with BDI3000 attached when I've tried to set these bits to zero 69 * (UART doesn't work after the 'reset run' command). 70 */ 71 #define CONFIG_SYS_HRCW_HIGH (\ 72 HRCWH_PCI_HOST |\ 73 HRCWH_PCI1_ARBITER_ENABLE |\ 74 HRCWH_CORE_ENABLE |\ 75 HRCWH_FROM_0XFFF00100 |\ 76 HRCWH_BOOTSEQ_DISABLE |\ 77 HRCWH_SW_WATCHDOG_DISABLE |\ 78 HRCWH_ROM_LOC_LOCAL_16BIT |\ 79 HRCWH_RL_EXT_LEGACY |\ 80 HRCWH_TSEC1M_IN_RGMII |\ 81 HRCWH_TSEC2M_IN_RGMII |\ 82 HRCWH_BIG_ENDIAN) 83 84 /* 85 * System IO Config 86 */ 87 #define CONFIG_SYS_SICRH (\ 88 SICRH_ESDHC_A_SD |\ 89 SICRH_ESDHC_B_SD |\ 90 SICRH_ESDHC_C_SD |\ 91 SICRH_GPIO_A_GPIO |\ 92 SICRH_GPIO_B_GPIO |\ 93 SICRH_IEEE1588_A_GPIO |\ 94 SICRH_USB |\ 95 SICRH_GTM_GPIO |\ 96 SICRH_IEEE1588_B_GPIO |\ 97 SICRH_ETSEC2_GPIO |\ 98 SICRH_GPIOSEL_1 |\ 99 SICRH_TMROBI_V3P3 |\ 100 SICRH_TSOBI1_V2P5 |\ 101 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 102 #define CONFIG_SYS_SICRL (\ 103 SICRL_SPI_PF0 |\ 104 SICRL_UART_PF0 |\ 105 SICRL_IRQ_PF0 |\ 106 SICRL_I2C2_PF0 |\ 107 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 108 109 /* 110 * IMMR new address 111 */ 112 #define CONFIG_SYS_IMMR 0xE0000000 113 114 /* 115 * SERDES 116 */ 117 #define CONFIG_FSL_SERDES 118 #define CONFIG_FSL_SERDES1 0xe3000 119 120 /* 121 * Arbiter Setup 122 */ 123 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 124 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 125 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 126 127 /* 128 * DDR Setup 129 */ 130 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 132 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 133 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 134 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 135 | DDRCDR_PZ_LOZ \ 136 | DDRCDR_NZ_LOZ \ 137 | DDRCDR_ODT \ 138 | DDRCDR_Q_DRN) 139 /* 0x7b880001 */ 140 /* 141 * Manually set up DDR parameters 142 * consist of one chip NT5TU64M16HG from NANYA 143 */ 144 145 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 146 147 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 148 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 149 | CSCONFIG_ODT_RD_NEVER \ 150 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 151 | CSCONFIG_BANK_BIT_3 \ 152 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 153 /* 0x80010102 */ 154 #define CONFIG_SYS_DDR_TIMING_3 0 155 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 156 | (0 << TIMING_CFG0_WRT_SHIFT) \ 157 | (0 << TIMING_CFG0_RRT_SHIFT) \ 158 | (0 << TIMING_CFG0_WWT_SHIFT) \ 159 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 160 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 161 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 162 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 163 /* 0x00260802 */ 164 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 165 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 166 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 167 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 168 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 169 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 170 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 171 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 172 /* 0x26279222 */ 173 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 174 | (4 << TIMING_CFG2_CPO_SHIFT) \ 175 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 176 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 177 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 178 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 179 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 180 /* 0x021848c5 */ 181 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 182 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 183 /* 0x08240100 */ 184 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 185 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 186 | SDRAM_CFG_DBW_16) 187 /* 0x43100000 */ 188 189 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 190 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 191 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 192 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 193 #define CONFIG_SYS_DDR_MODE2 0x00000000 194 195 /* 196 * Memory test 197 */ 198 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 199 #define CONFIG_SYS_MEMTEST_END 0x07f00000 200 201 /* 202 * The reserved memory 203 */ 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 205 206 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 207 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 208 209 /* 210 * Initial RAM Base Address Setup 211 */ 212 #define CONFIG_SYS_INIT_RAM_LOCK 1 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 214 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 215 #define CONFIG_SYS_GBL_DATA_OFFSET \ 216 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 217 218 /* 219 * Local Bus Configuration & Clock Setup 220 */ 221 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 222 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 223 #define CONFIG_SYS_LBC_LBCR 0x00040000 224 225 /* 226 * FLASH on the Local Bus 227 */ 228 #if 1 229 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 230 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 231 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 232 #define CONFIG_FLASH_CFI_LEGACY 233 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 234 #else 235 #define CONFIG_SYS_NO_FLASH 236 #endif 237 238 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 239 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 240 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 241 242 /* Window base at flash base */ 243 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 244 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 245 246 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 247 | BR_PS_16 /* 16 bit port */ \ 248 | BR_MS_GPCM /* MSEL = GPCM */ \ 249 | BR_V) /* valid */ 250 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 251 | OR_UPM_XAM \ 252 | OR_GPCM_CSNT \ 253 | OR_GPCM_ACS_DIV2 \ 254 | OR_GPCM_XACS \ 255 | OR_GPCM_SCY_15 \ 256 | OR_GPCM_TRLX_SET \ 257 | OR_GPCM_EHTR_SET) 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 135 261 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 265 /* 266 * FPGA 267 */ 268 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 269 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 270 271 /* Window base at FPGA base */ 272 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 273 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 274 275 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 276 | BR_PS_16 /* 16 bit port */ \ 277 | BR_MS_GPCM /* MSEL = GPCM */ \ 278 | BR_V) /* valid */ 279 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 280 | OR_UPM_XAM \ 281 | OR_GPCM_CSNT \ 282 | OR_GPCM_ACS_DIV2 \ 283 | OR_GPCM_XACS \ 284 | OR_GPCM_SCY_15 \ 285 | OR_GPCM_TRLX_SET \ 286 | OR_GPCM_EHTR_SET) 287 288 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 289 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 290 291 #define CONFIG_SYS_FPGA_COUNT 1 292 293 #define CONFIG_SYS_MCLINK_MAX 3 294 295 #define CONFIG_SYS_FPGA_PTR \ 296 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 297 298 /* 299 * Serial Port 300 */ 301 #define CONFIG_CONS_INDEX 2 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 311 312 /* Pass open firmware flat tree */ 313 314 /* I2C */ 315 #define CONFIG_SYS_I2C 316 #define CONFIG_SYS_I2C_FSL 317 #define CONFIG_SYS_FSL_I2C_SPEED 400000 318 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 320 321 #define CONFIG_PCA953X /* NXP PCA9554 */ 322 #define CONFIG_PCA9698 /* NXP PCA9698 */ 323 324 #define CONFIG_SYS_I2C_IHS 325 #define CONFIG_SYS_I2C_IHS_CH0 326 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 327 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 328 #define CONFIG_SYS_I2C_IHS_CH1 329 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 330 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 331 #define CONFIG_SYS_I2C_IHS_CH2 332 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 333 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 334 #define CONFIG_SYS_I2C_IHS_CH3 335 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 336 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 337 338 #ifdef CONFIG_HRCON_DH 339 #define CONFIG_SYS_I2C_IHS_DUAL 340 #define CONFIG_SYS_I2C_IHS_CH0_1 341 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 342 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 343 #define CONFIG_SYS_I2C_IHS_CH1_1 344 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 345 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 346 #define CONFIG_SYS_I2C_IHS_CH2_1 347 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 348 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 349 #define CONFIG_SYS_I2C_IHS_CH3_1 350 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 351 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 352 #endif 353 354 /* 355 * Software (bit-bang) I2C driver configuration 356 */ 357 #define CONFIG_SYS_I2C_SOFT 358 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 359 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 360 #define I2C_SOFT_DECLARATIONS2 361 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 362 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 363 #define I2C_SOFT_DECLARATIONS3 364 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 365 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 366 #define I2C_SOFT_DECLARATIONS4 367 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 368 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 369 #define I2C_SOFT_DECLARATIONS5 370 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 371 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 372 #define I2C_SOFT_DECLARATIONS6 373 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 374 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 375 #define I2C_SOFT_DECLARATIONS7 376 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 378 #define I2C_SOFT_DECLARATIONS8 379 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 380 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 381 382 #ifdef CONFIG_HRCON_DH 383 #define I2C_SOFT_DECLARATIONS9 384 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 385 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 386 #define I2C_SOFT_DECLARATIONS10 387 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 388 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 389 #define I2C_SOFT_DECLARATIONS11 390 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 391 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 392 #define I2C_SOFT_DECLARATIONS12 393 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 394 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 395 #endif 396 397 #ifdef CONFIG_HRCON_DH 398 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 399 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 400 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 401 {12, 0x4c} } 402 #else 403 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 404 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 405 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 406 {8, 0x4c} } 407 #endif 408 409 #ifndef __ASSEMBLY__ 410 void fpga_gpio_set(unsigned int bus, int pin); 411 void fpga_gpio_clear(unsigned int bus, int pin); 412 int fpga_gpio_get(unsigned int bus, int pin); 413 void fpga_control_set(unsigned int bus, int pin); 414 void fpga_control_clear(unsigned int bus, int pin); 415 #endif 416 417 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 418 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 419 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 420 421 #ifdef CONFIG_HRCON_DH 422 #define I2C_ACTIVE \ 423 do { \ 424 if (I2C_ADAP_HWNR > 7) \ 425 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 426 else \ 427 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 428 } while (0) 429 #else 430 #define I2C_ACTIVE { } 431 #endif 432 #define I2C_TRISTATE { } 433 #define I2C_READ \ 434 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 435 #define I2C_SDA(bit) \ 436 do { \ 437 if (bit) \ 438 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 439 else \ 440 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 441 } while (0) 442 #define I2C_SCL(bit) \ 443 do { \ 444 if (bit) \ 445 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 446 else \ 447 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 448 } while (0) 449 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 450 451 /* 452 * Software (bit-bang) MII driver configuration 453 */ 454 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 455 #define CONFIG_BITBANGMII_MULTI 456 457 /* 458 * OSD Setup 459 */ 460 #define CONFIG_SYS_OSD_SCREENS 1 461 #define CONFIG_SYS_DP501_DIFFERENTIAL 462 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 463 464 #ifdef CONFIG_HRCON_DH 465 #define CONFIG_SYS_OSD_DH 466 #endif 467 468 /* 469 * General PCI 470 * Addresses are mapped 1-1. 471 */ 472 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 473 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 474 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 475 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 476 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 477 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 478 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 480 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 481 482 /* enable PCIE clock */ 483 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 484 485 #define CONFIG_PCI 486 #define CONFIG_PCI_INDIRECT_BRIDGE 487 #define CONFIG_PCIE 488 489 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 490 491 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 492 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 493 494 /* 495 * TSEC 496 */ 497 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 498 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 499 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 500 501 /* 502 * TSEC ethernet configuration 503 */ 504 #define CONFIG_MII 1 /* MII PHY management */ 505 #define CONFIG_TSEC1 506 #define CONFIG_TSEC1_NAME "eTSEC0" 507 #define TSEC1_PHY_ADDR 1 508 #define TSEC1_PHYIDX 0 509 #define TSEC1_FLAGS TSEC_GIGABIT 510 511 /* Options are: eTSEC[0-1] */ 512 #define CONFIG_ETHPRIME "eTSEC0" 513 514 /* 515 * Environment 516 */ 517 #if 1 518 #define CONFIG_ENV_IS_IN_FLASH 1 519 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 520 CONFIG_SYS_MONITOR_LEN) 521 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 522 #define CONFIG_ENV_SIZE 0x2000 523 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 524 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 525 #else 526 #define CONFIG_ENV_IS_NOWHERE 527 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 528 #endif 529 530 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 531 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 532 533 /* 534 * Command line configuration. 535 */ 536 #define CONFIG_CMD_MII 537 #define CONFIG_CMD_PCI 538 539 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 540 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 541 542 /* 543 * Miscellaneous configurable options 544 */ 545 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 546 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 547 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 548 549 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 550 551 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 552 553 #define CONFIG_SYS_CONSOLE_INFO_QUIET 554 555 /* Print Buffer Size */ 556 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 557 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 558 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 559 560 /* 561 * For booting Linux, the board info and command line data 562 * have to be in the first 256 MB of memory, since this is 563 * the maximum mapped by the Linux kernel during initialization. 564 */ 565 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 566 567 /* 568 * Core HID Setup 569 */ 570 #define CONFIG_SYS_HID0_INIT 0x000000000 571 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 572 HID0_ENABLE_INSTRUCTION_CACHE | \ 573 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 574 #define CONFIG_SYS_HID2 HID2_HBE 575 576 /* 577 * MMU Setup 578 */ 579 580 /* DDR: cache cacheable */ 581 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 582 BATL_MEMCOHERENCE) 583 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 584 BATU_VS | BATU_VP) 585 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 586 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 587 588 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 589 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 590 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 591 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 592 BATU_VP) 593 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 594 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 595 596 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 597 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 598 BATL_MEMCOHERENCE) 599 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 600 BATU_VS | BATU_VP) 601 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 602 BATL_CACHEINHIBIT | \ 603 BATL_GUARDEDSTORAGE) 604 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 605 606 /* Stack in dcache: cacheable, no memory coherence */ 607 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 608 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 609 BATU_VS | BATU_VP) 610 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 611 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 612 613 /* 614 * Environment Configuration 615 */ 616 617 #define CONFIG_ENV_OVERWRITE 618 619 #if defined(CONFIG_TSEC_ENET) 620 #define CONFIG_HAS_ETH0 621 #endif 622 623 #define CONFIG_BAUDRATE 115200 624 625 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 626 627 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 628 629 #define CONFIG_HOSTNAME hrcon 630 #define CONFIG_ROOTPATH "/opt/nfsroot" 631 #define CONFIG_BOOTFILE "uImage" 632 633 #define CONFIG_PREBOOT /* enable preboot variable */ 634 635 #define CONFIG_EXTRA_ENV_SETTINGS \ 636 "netdev=eth0\0" \ 637 "consoledev=ttyS1\0" \ 638 "u-boot=u-boot.bin\0" \ 639 "kernel_addr=1000000\0" \ 640 "fdt_addr=C00000\0" \ 641 "fdtfile=hrcon.dtb\0" \ 642 "load=tftp ${loadaddr} ${u-boot}\0" \ 643 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 644 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 645 " +${filesize};cp.b ${fileaddr} " \ 646 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 647 "upd=run load update\0" \ 648 649 #define CONFIG_NFSBOOTCOMMAND \ 650 "setenv bootargs root=/dev/nfs rw " \ 651 "nfsroot=$serverip:$rootpath " \ 652 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 653 "console=$consoledev,$baudrate $othbootargs;" \ 654 "tftp ${kernel_addr} $bootfile;" \ 655 "tftp ${fdt_addr} $fdtfile;" \ 656 "bootm ${kernel_addr} - ${fdt_addr}" 657 658 #define CONFIG_MMCBOOTCOMMAND \ 659 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 660 "console=$consoledev,$baudrate $othbootargs;" \ 661 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 662 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 663 "bootm ${kernel_addr} - ${fdt_addr}" 664 665 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 666 667 #endif /* __CONFIG_H */ 668