1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #ifdef CONFIG_HRCON_DH 24 #define CONFIG_IDENT_STRING " hrcon dh 0.01" 25 #else 26 #define CONFIG_IDENT_STRING " hrcon 0.01" 27 #endif 28 29 30 #define CONFIG_BOARD_EARLY_INIT_F 31 #define CONFIG_BOARD_EARLY_INIT_R 32 #define CONFIG_LAST_STAGE_INIT 33 34 /* new uImage format support */ 35 #define CONFIG_FIT 1 36 #define CONFIG_FIT_VERBOSE 1 37 38 #define CONFIG_MMC 39 #define CONFIG_FSL_ESDHC 40 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 41 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 42 43 #define CONFIG_CMD_MMC 44 #define CONFIG_GENERIC_MMC 45 #define CONFIG_DOS_PARTITION 46 #define CONFIG_CMD_EXT2 47 48 #define CONFIG_CMD_FPGAD 49 #define CONFIG_CMD_IOLOOP 50 51 /* 52 * System Clock Setup 53 */ 54 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 55 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 56 57 /* 58 * Hardware Reset Configuration Word 59 * if CLKIN is 66.66MHz, then 60 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 61 * We choose the A type silicon as default, so the core is 400Mhz. 62 */ 63 #define CONFIG_SYS_HRCW_LOW (\ 64 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 65 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 66 HRCWL_SVCOD_DIV_2 |\ 67 HRCWL_CSB_TO_CLKIN_4X1 |\ 68 HRCWL_CORE_TO_CSB_3X1) 69 /* 70 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 71 * in 8308's HRCWH according to the manual, but original Freescale's 72 * code has them and I've expirienced some problems using the board 73 * with BDI3000 attached when I've tried to set these bits to zero 74 * (UART doesn't work after the 'reset run' command). 75 */ 76 #define CONFIG_SYS_HRCW_HIGH (\ 77 HRCWH_PCI_HOST |\ 78 HRCWH_PCI1_ARBITER_ENABLE |\ 79 HRCWH_CORE_ENABLE |\ 80 HRCWH_FROM_0XFFF00100 |\ 81 HRCWH_BOOTSEQ_DISABLE |\ 82 HRCWH_SW_WATCHDOG_DISABLE |\ 83 HRCWH_ROM_LOC_LOCAL_16BIT |\ 84 HRCWH_RL_EXT_LEGACY |\ 85 HRCWH_TSEC1M_IN_RGMII |\ 86 HRCWH_TSEC2M_IN_RGMII |\ 87 HRCWH_BIG_ENDIAN) 88 89 /* 90 * System IO Config 91 */ 92 #define CONFIG_SYS_SICRH (\ 93 SICRH_ESDHC_A_SD |\ 94 SICRH_ESDHC_B_SD |\ 95 SICRH_ESDHC_C_SD |\ 96 SICRH_GPIO_A_GPIO |\ 97 SICRH_GPIO_B_GPIO |\ 98 SICRH_IEEE1588_A_GPIO |\ 99 SICRH_USB |\ 100 SICRH_GTM_GPIO |\ 101 SICRH_IEEE1588_B_GPIO |\ 102 SICRH_ETSEC2_GPIO |\ 103 SICRH_GPIOSEL_1 |\ 104 SICRH_TMROBI_V3P3 |\ 105 SICRH_TSOBI1_V2P5 |\ 106 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 107 #define CONFIG_SYS_SICRL (\ 108 SICRL_SPI_PF0 |\ 109 SICRL_UART_PF0 |\ 110 SICRL_IRQ_PF0 |\ 111 SICRL_I2C2_PF0 |\ 112 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 113 114 /* 115 * IMMR new address 116 */ 117 #define CONFIG_SYS_IMMR 0xE0000000 118 119 /* 120 * SERDES 121 */ 122 #define CONFIG_FSL_SERDES 123 #define CONFIG_FSL_SERDES1 0xe3000 124 125 /* 126 * Arbiter Setup 127 */ 128 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 129 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 130 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 131 132 /* 133 * DDR Setup 134 */ 135 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 137 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 138 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 139 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 140 | DDRCDR_PZ_LOZ \ 141 | DDRCDR_NZ_LOZ \ 142 | DDRCDR_ODT \ 143 | DDRCDR_Q_DRN) 144 /* 0x7b880001 */ 145 /* 146 * Manually set up DDR parameters 147 * consist of one chip NT5TU64M16HG from NANYA 148 */ 149 150 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 151 152 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 153 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 154 | CSCONFIG_ODT_RD_NEVER \ 155 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 156 | CSCONFIG_BANK_BIT_3 \ 157 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 158 /* 0x80010102 */ 159 #define CONFIG_SYS_DDR_TIMING_3 0 160 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 161 | (0 << TIMING_CFG0_WRT_SHIFT) \ 162 | (0 << TIMING_CFG0_RRT_SHIFT) \ 163 | (0 << TIMING_CFG0_WWT_SHIFT) \ 164 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 165 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 166 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 167 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 168 /* 0x00260802 */ 169 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 170 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 171 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 172 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 173 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 174 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 175 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 176 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 177 /* 0x26279222 */ 178 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 179 | (4 << TIMING_CFG2_CPO_SHIFT) \ 180 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 181 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 182 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 183 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 184 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 185 /* 0x021848c5 */ 186 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 187 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 188 /* 0x08240100 */ 189 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 190 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 191 | SDRAM_CFG_DBW_16) 192 /* 0x43100000 */ 193 194 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 195 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 196 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 197 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 198 #define CONFIG_SYS_DDR_MODE2 0x00000000 199 200 /* 201 * Memory test 202 */ 203 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 204 #define CONFIG_SYS_MEMTEST_END 0x07f00000 205 206 /* 207 * The reserved memory 208 */ 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 210 211 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 212 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 213 214 /* 215 * Initial RAM Base Address Setup 216 */ 217 #define CONFIG_SYS_INIT_RAM_LOCK 1 218 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 219 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 220 #define CONFIG_SYS_GBL_DATA_OFFSET \ 221 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 222 223 /* 224 * Local Bus Configuration & Clock Setup 225 */ 226 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 227 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 228 #define CONFIG_SYS_LBC_LBCR 0x00040000 229 230 /* 231 * FLASH on the Local Bus 232 */ 233 #if 1 234 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 235 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 236 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 237 #define CONFIG_FLASH_CFI_LEGACY 238 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 239 #else 240 #define CONFIG_SYS_NO_FLASH 241 #endif 242 243 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 244 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 245 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 246 247 /* Window base at flash base */ 248 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 249 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 250 251 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 252 | BR_PS_16 /* 16 bit port */ \ 253 | BR_MS_GPCM /* MSEL = GPCM */ \ 254 | BR_V) /* valid */ 255 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 256 | OR_UPM_XAM \ 257 | OR_GPCM_CSNT \ 258 | OR_GPCM_ACS_DIV2 \ 259 | OR_GPCM_XACS \ 260 | OR_GPCM_SCY_15 \ 261 | OR_GPCM_TRLX_SET \ 262 | OR_GPCM_EHTR_SET) 263 264 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265 #define CONFIG_SYS_MAX_FLASH_SECT 135 266 267 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 270 /* 271 * FPGA 272 */ 273 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 274 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 275 276 /* Window base at FPGA base */ 277 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 278 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 279 280 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 281 | BR_PS_16 /* 16 bit port */ \ 282 | BR_MS_GPCM /* MSEL = GPCM */ \ 283 | BR_V) /* valid */ 284 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 285 | OR_UPM_XAM \ 286 | OR_GPCM_CSNT \ 287 | OR_GPCM_ACS_DIV2 \ 288 | OR_GPCM_XACS \ 289 | OR_GPCM_SCY_15 \ 290 | OR_GPCM_TRLX_SET \ 291 | OR_GPCM_EHTR_SET) 292 293 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 294 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 295 296 #define CONFIG_SYS_FPGA_COUNT 1 297 298 #define CONFIG_SYS_MCLINK_MAX 3 299 300 #define CONFIG_SYS_FPGA_PTR \ 301 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 302 303 /* 304 * Serial Port 305 */ 306 #define CONFIG_CONS_INDEX 2 307 #define CONFIG_SYS_NS16550_SERIAL 308 #define CONFIG_SYS_NS16550_REG_SIZE 1 309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 310 311 #define CONFIG_SYS_BAUDRATE_TABLE \ 312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 313 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 316 317 /* Use the HUSH parser */ 318 #define CONFIG_SYS_HUSH_PARSER 319 320 /* Pass open firmware flat tree */ 321 #define CONFIG_OF_BOARD_SETUP 1 322 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 323 324 /* I2C */ 325 #define CONFIG_SYS_I2C 326 #define CONFIG_SYS_I2C_FSL 327 #define CONFIG_SYS_FSL_I2C_SPEED 400000 328 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 329 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 330 331 #define CONFIG_PCA953X /* NXP PCA9554 */ 332 #define CONFIG_PCA9698 /* NXP PCA9698 */ 333 334 #define CONFIG_SYS_I2C_IHS 335 #define CONFIG_SYS_I2C_IHS_CH0 336 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 337 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 338 #define CONFIG_SYS_I2C_IHS_CH1 339 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 340 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 341 #define CONFIG_SYS_I2C_IHS_CH2 342 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 343 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 344 #define CONFIG_SYS_I2C_IHS_CH3 345 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 346 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 347 348 #ifdef CONFIG_HRCON_DH 349 #define CONFIG_SYS_I2C_IHS_DUAL 350 #define CONFIG_SYS_I2C_IHS_CH0_1 351 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 352 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 353 #define CONFIG_SYS_I2C_IHS_CH1_1 354 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 355 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 356 #define CONFIG_SYS_I2C_IHS_CH2_1 357 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 358 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 359 #define CONFIG_SYS_I2C_IHS_CH3_1 360 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 361 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 362 #endif 363 364 /* 365 * Software (bit-bang) I2C driver configuration 366 */ 367 #define CONFIG_SYS_I2C_SOFT 368 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 370 #define I2C_SOFT_DECLARATIONS2 371 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 373 #define I2C_SOFT_DECLARATIONS3 374 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 375 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 376 #define I2C_SOFT_DECLARATIONS4 377 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 378 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 379 #define I2C_SOFT_DECLARATIONS5 380 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 381 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 382 #define I2C_SOFT_DECLARATIONS6 383 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 384 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 385 #define I2C_SOFT_DECLARATIONS7 386 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 387 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 388 #define I2C_SOFT_DECLARATIONS8 389 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 390 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 391 392 #ifdef CONFIG_HRCON_DH 393 #define I2C_SOFT_DECLARATIONS9 394 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 395 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 396 #define I2C_SOFT_DECLARATIONS10 397 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 398 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 399 #define I2C_SOFT_DECLARATIONS11 400 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 401 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 402 #define I2C_SOFT_DECLARATIONS12 403 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 404 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 405 #endif 406 407 #ifdef CONFIG_HRCON_DH 408 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 409 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 410 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 411 {12, 0x4c} } 412 #else 413 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 414 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 415 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 416 {8, 0x4c} } 417 #endif 418 419 #ifndef __ASSEMBLY__ 420 void fpga_gpio_set(unsigned int bus, int pin); 421 void fpga_gpio_clear(unsigned int bus, int pin); 422 int fpga_gpio_get(unsigned int bus, int pin); 423 void fpga_control_set(unsigned int bus, int pin); 424 void fpga_control_clear(unsigned int bus, int pin); 425 #endif 426 427 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 428 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 429 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 430 431 #ifdef CONFIG_HRCON_DH 432 #define I2C_ACTIVE \ 433 do { \ 434 if (I2C_ADAP_HWNR > 7) \ 435 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 436 else \ 437 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 438 } while (0) 439 #else 440 #define I2C_ACTIVE { } 441 #endif 442 #define I2C_TRISTATE { } 443 #define I2C_READ \ 444 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 445 #define I2C_SDA(bit) \ 446 do { \ 447 if (bit) \ 448 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 449 else \ 450 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 451 } while (0) 452 #define I2C_SCL(bit) \ 453 do { \ 454 if (bit) \ 455 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 456 else \ 457 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 458 } while (0) 459 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 460 461 /* 462 * Software (bit-bang) MII driver configuration 463 */ 464 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 465 #define CONFIG_BITBANGMII_MULTI 466 467 /* 468 * OSD Setup 469 */ 470 #define CONFIG_SYS_OSD_SCREENS 1 471 #define CONFIG_SYS_DP501_DIFFERENTIAL 472 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 473 474 #ifdef CONFIG_HRCON_DH 475 #define CONFIG_SYS_OSD_DH 476 #endif 477 478 /* 479 * General PCI 480 * Addresses are mapped 1-1. 481 */ 482 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 483 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 485 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 486 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 487 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 488 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 489 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 490 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 491 492 /* enable PCIE clock */ 493 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 494 495 #define CONFIG_PCI 496 #define CONFIG_PCI_INDIRECT_BRIDGE 497 #define CONFIG_PCIE 498 499 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 500 501 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 502 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 503 504 /* 505 * TSEC 506 */ 507 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 508 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 509 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 510 511 /* 512 * TSEC ethernet configuration 513 */ 514 #define CONFIG_MII 1 /* MII PHY management */ 515 #define CONFIG_TSEC1 516 #define CONFIG_TSEC1_NAME "eTSEC0" 517 #define TSEC1_PHY_ADDR 1 518 #define TSEC1_PHYIDX 0 519 #define TSEC1_FLAGS TSEC_GIGABIT 520 521 /* Options are: eTSEC[0-1] */ 522 #define CONFIG_ETHPRIME "eTSEC0" 523 524 /* 525 * Environment 526 */ 527 #if 1 528 #define CONFIG_ENV_IS_IN_FLASH 1 529 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 530 CONFIG_SYS_MONITOR_LEN) 531 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 532 #define CONFIG_ENV_SIZE 0x2000 533 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 534 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 535 #else 536 #define CONFIG_ENV_IS_NOWHERE 537 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 538 #endif 539 540 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 541 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 542 543 /* 544 * Command line configuration. 545 */ 546 #define CONFIG_CMD_I2C 547 #define CONFIG_CMD_MII 548 #define CONFIG_CMD_PCI 549 #define CONFIG_CMD_PING 550 551 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 552 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 553 554 /* 555 * Miscellaneous configurable options 556 */ 557 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 558 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 559 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 560 561 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 562 563 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 564 565 #define CONFIG_SYS_CONSOLE_INFO_QUIET 566 567 /* Print Buffer Size */ 568 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 569 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 571 572 /* 573 * For booting Linux, the board info and command line data 574 * have to be in the first 256 MB of memory, since this is 575 * the maximum mapped by the Linux kernel during initialization. 576 */ 577 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 578 579 /* 580 * Core HID Setup 581 */ 582 #define CONFIG_SYS_HID0_INIT 0x000000000 583 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 584 HID0_ENABLE_INSTRUCTION_CACHE | \ 585 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 586 #define CONFIG_SYS_HID2 HID2_HBE 587 588 /* 589 * MMU Setup 590 */ 591 592 /* DDR: cache cacheable */ 593 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 594 BATL_MEMCOHERENCE) 595 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 596 BATU_VS | BATU_VP) 597 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 598 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 599 600 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 601 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 602 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 603 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 604 BATU_VP) 605 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 606 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 607 608 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 609 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 610 BATL_MEMCOHERENCE) 611 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 612 BATU_VS | BATU_VP) 613 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 614 BATL_CACHEINHIBIT | \ 615 BATL_GUARDEDSTORAGE) 616 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 617 618 /* Stack in dcache: cacheable, no memory coherence */ 619 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 620 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 621 BATU_VS | BATU_VP) 622 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 623 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 624 625 /* 626 * Environment Configuration 627 */ 628 629 #define CONFIG_ENV_OVERWRITE 630 631 #if defined(CONFIG_TSEC_ENET) 632 #define CONFIG_HAS_ETH0 633 #endif 634 635 #define CONFIG_BAUDRATE 115200 636 637 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 638 639 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 640 641 #define CONFIG_HOSTNAME hrcon 642 #define CONFIG_ROOTPATH "/opt/nfsroot" 643 #define CONFIG_BOOTFILE "uImage" 644 645 #define CONFIG_PREBOOT /* enable preboot variable */ 646 647 #define CONFIG_EXTRA_ENV_SETTINGS \ 648 "netdev=eth0\0" \ 649 "consoledev=ttyS1\0" \ 650 "u-boot=u-boot.bin\0" \ 651 "kernel_addr=1000000\0" \ 652 "fdt_addr=C00000\0" \ 653 "fdtfile=hrcon.dtb\0" \ 654 "load=tftp ${loadaddr} ${u-boot}\0" \ 655 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 656 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 657 " +${filesize};cp.b ${fileaddr} " \ 658 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 659 "upd=run load update\0" \ 660 661 #define CONFIG_NFSBOOTCOMMAND \ 662 "setenv bootargs root=/dev/nfs rw " \ 663 "nfsroot=$serverip:$rootpath " \ 664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 665 "console=$consoledev,$baudrate $othbootargs;" \ 666 "tftp ${kernel_addr} $bootfile;" \ 667 "tftp ${fdt_addr} $fdtfile;" \ 668 "bootm ${kernel_addr} - ${fdt_addr}" 669 670 #define CONFIG_MMCBOOTCOMMAND \ 671 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 674 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 675 "bootm ${kernel_addr} - ${fdt_addr}" 676 677 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 678 679 680 #endif /* __CONFIG_H */ 681