1*afee3fb8SBin Meng /* 2*afee3fb8SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*afee3fb8SBin Meng * 4*afee3fb8SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*afee3fb8SBin Meng */ 6*afee3fb8SBin Meng 7*afee3fb8SBin Meng /* 8*afee3fb8SBin Meng * board/config.h - configuration options, board specific 9*afee3fb8SBin Meng */ 10*afee3fb8SBin Meng 11*afee3fb8SBin Meng #ifndef __CONFIG_H 12*afee3fb8SBin Meng #define __CONFIG_H 13*afee3fb8SBin Meng 14*afee3fb8SBin Meng #include <configs/x86-common.h> 15*afee3fb8SBin Meng 16*afee3fb8SBin Meng #define CONFIG_SYS_MONITOR_LEN (1 << 20) 17*afee3fb8SBin Meng #define CONFIG_BOARD_EARLY_INIT_F 18*afee3fb8SBin Meng 19*afee3fb8SBin Meng #define CONFIG_NR_DRAM_BANKS 1 20*afee3fb8SBin Meng 21*afee3fb8SBin Meng #define CONFIG_X86_SERIAL 22*afee3fb8SBin Meng 23*afee3fb8SBin Meng /* ns16550 UART is memory-mapped in Quark SoC */ 24*afee3fb8SBin Meng #undef CONFIG_SYS_NS16550_PORT_MAPPED 25*afee3fb8SBin Meng 26*afee3fb8SBin Meng #define CONFIG_PCI_MEM_BUS 0x90000000 27*afee3fb8SBin Meng #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 28*afee3fb8SBin Meng #define CONFIG_PCI_MEM_SIZE 0x20000000 29*afee3fb8SBin Meng 30*afee3fb8SBin Meng #define CONFIG_PCI_PREF_BUS 0xb0000000 31*afee3fb8SBin Meng #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS 32*afee3fb8SBin Meng #define CONFIG_PCI_PREF_SIZE 0x20000000 33*afee3fb8SBin Meng 34*afee3fb8SBin Meng #define CONFIG_PCI_IO_BUS 0x2000 35*afee3fb8SBin Meng #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 36*afee3fb8SBin Meng #define CONFIG_PCI_IO_SIZE 0xe000 37*afee3fb8SBin Meng 38*afee3fb8SBin Meng #define CONFIG_SYS_EARLY_PCI_INIT 39*afee3fb8SBin Meng #define CONFIG_PCI_PNP 40*afee3fb8SBin Meng 41*afee3fb8SBin Meng #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ 42*afee3fb8SBin Meng "stdout=serial\0" \ 43*afee3fb8SBin Meng "stderr=serial\0" 44*afee3fb8SBin Meng 45*afee3fb8SBin Meng /* SATA is not supported in Quark SoC */ 46*afee3fb8SBin Meng #undef CONFIG_SCSI_AHCI 47*afee3fb8SBin Meng #undef CONFIG_CMD_SCSI 48*afee3fb8SBin Meng 49*afee3fb8SBin Meng /* Video is not supported in Quark SoC */ 50*afee3fb8SBin Meng #undef CONFIG_VIDEO 51*afee3fb8SBin Meng #undef CONFIG_CFB_CONSOLE 52*afee3fb8SBin Meng 53*afee3fb8SBin Meng #endif /* __CONFIG_H */ 54