xref: /rk3399_rockchip-uboot/include/configs/exynos5420-common.h (revision 87033d4d97e0cc569c59efef7ce4ce940c48e71b)
1*87033d4dSSimon Glass /*
2*87033d4dSSimon Glass  * Copyright (C) 2013 Samsung Electronics
3*87033d4dSSimon Glass  *
4*87033d4dSSimon Glass  * Configuration settings for the SAMSUNG EXYNOS5420 SoC
5*87033d4dSSimon Glass  *
6*87033d4dSSimon Glass  * SPDX-License-Identifier:	GPL-2.0+
7*87033d4dSSimon Glass  */
8*87033d4dSSimon Glass 
9*87033d4dSSimon Glass #ifndef __CONFIG_EXYNOS5420_H
10*87033d4dSSimon Glass #define __CONFIG_EXYNOS5420_H
11*87033d4dSSimon Glass 
12*87033d4dSSimon Glass #define CONFIG_EXYNOS5420
13*87033d4dSSimon Glass 
14*87033d4dSSimon Glass #include <configs/exynos5-common.h>
15*87033d4dSSimon Glass 
16*87033d4dSSimon Glass #define MACH_TYPE_SMDK5420	8002
17*87033d4dSSimon Glass #define CONFIG_MACH_TYPE	MACH_TYPE_SMDK5420
18*87033d4dSSimon Glass 
19*87033d4dSSimon Glass #define CONFIG_VAR_SIZE_SPL
20*87033d4dSSimon Glass 
21*87033d4dSSimon Glass #define CONFIG_SYS_SDRAM_BASE		0x20000000
22*87033d4dSSimon Glass #define CONFIG_SYS_TEXT_BASE		0x23E00000
23*87033d4dSSimon Glass #ifdef CONFIG_VAR_SIZE_SPL
24*87033d4dSSimon Glass #define CONFIG_SPL_TEXT_BASE		0x02024410
25*87033d4dSSimon Glass #else
26*87033d4dSSimon Glass #define CONFIG_SPL_TEXT_BASE		0x02024400
27*87033d4dSSimon Glass #endif
28*87033d4dSSimon Glass #define CONFIG_IRAM_TOP			0x02074000
29*87033d4dSSimon Glass 
30*87033d4dSSimon Glass #define CONFIG_SPL_MAX_FOOTPRINT	(30 * 1024)
31*87033d4dSSimon Glass 
32*87033d4dSSimon Glass #define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
33*87033d4dSSimon Glass 
34*87033d4dSSimon Glass #define CONFIG_MAX_I2C_NUM	11
35*87033d4dSSimon Glass 
36*87033d4dSSimon Glass #define CONFIG_BOARD_REV_GPIO_COUNT	2
37*87033d4dSSimon Glass 
38*87033d4dSSimon Glass #define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
39*87033d4dSSimon Glass 
40*87033d4dSSimon Glass /*
41*87033d4dSSimon Glass  * Put the initial stack pointer 1KB below this to allow room for the
42*87033d4dSSimon Glass  * SPL marker. This value is arbitrary, but gd_t is placed starting here.
43*87033d4dSSimon Glass  */
44*87033d4dSSimon Glass #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
45*87033d4dSSimon Glass 
46*87033d4dSSimon Glass /* DRAM Memory Banks */
47*87033d4dSSimon Glass #define CONFIG_NR_DRAM_BANKS	7
48*87033d4dSSimon Glass #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
49*87033d4dSSimon Glass 
50*87033d4dSSimon Glass #endif	/* __CONFIG_EXYNOS5420_H */
51