1 /* 2 * Copyright (C) 2013 Samsung Electronics 3 * 4 * Configuration settings for the SAMSUNG EXYNOS5 board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_EXYNOS5_COMMON_H 10 #define __CONFIG_EXYNOS5_COMMON_H 11 12 #define CONFIG_EXYNOS5 /* Exynos5 Family */ 13 14 #include "exynos-common.h" 15 16 #define CONFIG_SYS_CACHELINE_SIZE 64 17 #define CONFIG_EXYNOS_SPL 18 19 /* Allow tracing to be enabled */ 20 #define CONFIG_TRACE 21 #define CONFIG_CMD_TRACE 22 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 23 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 24 #define CONFIG_TRACE_EARLY 25 #define CONFIG_TRACE_EARLY_ADDR 0x50000000 26 27 28 /* Enable ACE acceleration for SHA1 and SHA256 */ 29 #define CONFIG_EXYNOS_ACE_SHA 30 #define CONFIG_SHA_HW_ACCEL 31 32 /* Power Down Modes */ 33 #define S5P_CHECK_SLEEP 0x00000BAD 34 #define S5P_CHECK_DIDLE 0xBAD00000 35 #define S5P_CHECK_LPA 0xABAD0000 36 37 /* Offset for inform registers */ 38 #define INFORM0_OFFSET 0x800 39 #define INFORM1_OFFSET 0x804 40 #define INFORM2_OFFSET 0x808 41 #define INFORM3_OFFSET 0x80c 42 43 /* select serial console configuration */ 44 #define CONFIG_BAUDRATE 115200 45 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 46 #define CONFIG_SILENT_CONSOLE 47 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 48 #define CONFIG_CONSOLE_MUX 49 50 #define EXYNOS_DEVICE_SETTINGS \ 51 "stdin=serial\0" \ 52 "stdout=serial\0" \ 53 "stderr=serial\0" 54 55 #define CONFIG_EXTRA_ENV_SETTINGS \ 56 EXYNOS_DEVICE_SETTINGS 57 58 #define CONFIG_CMD_HASH 59 60 /* Thermal Management Unit */ 61 #define CONFIG_EXYNOS_TMU 62 #define CONFIG_CMD_DTT 63 #define CONFIG_TMU_CMD_DTT 64 65 /* TPM */ 66 #define CONFIG_TPM 67 #define CONFIG_CMD_TPM 68 #define CONFIG_TPM_TIS_I2C 69 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 70 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 71 72 /* MMC SPL */ 73 #define COPY_BL2_FNPTR_ADDR 0x02020030 74 #define CONFIG_SUPPORT_EMMC_BOOT 75 76 #define CONFIG_SPL_LIBCOMMON_SUPPORT 77 #define CONFIG_SPL_GPIO_SUPPORT 78 79 /* specific .lds file */ 80 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 81 82 /* Boot Argument Buffer Size */ 83 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 85 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 86 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 87 88 #define CONFIG_RD_LVL 89 90 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 91 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 92 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 93 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 94 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 95 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 96 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 97 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 98 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 99 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 100 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 101 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 102 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 103 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 104 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 105 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 106 107 #define CONFIG_SYS_MONITOR_BASE 0x00000000 108 109 #define CONFIG_SYS_MMC_ENV_DEV 0 110 111 #define CONFIG_SECURE_BL1_ONLY 112 113 /* Secure FW size configuration */ 114 #ifdef CONFIG_SECURE_BL1_ONLY 115 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 116 #else 117 #define CONFIG_SEC_FW_SIZE 0 118 #endif 119 120 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 121 #define CONFIG_RES_BLOCK_SIZE (512) 122 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 123 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 124 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 125 126 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 127 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 128 129 /* U-boot copy size from boot Media to DRAM.*/ 130 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 131 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 132 133 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 134 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) 135 136 /* I2C */ 137 #define CONFIG_SYS_I2C_INIT_BOARD 138 #define CONFIG_SYS_I2C 139 #define CONFIG_CMD_I2C 140 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ 141 #define CONFIG_SYS_I2C_S3C24X0 142 #define CONFIG_I2C_MULTI_BUS 143 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 144 #define CONFIG_I2C_EDID 145 146 /* SPI */ 147 #ifdef CONFIG_SPI_FLASH 148 #define CONFIG_EXYNOS_SPI 149 #define CONFIG_CMD_SF 150 #define CONFIG_CMD_SPI 151 #define CONFIG_SPI_FLASH_WINBOND 152 #define CONFIG_SPI_FLASH_GIGADEVICE 153 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 154 #define CONFIG_SF_DEFAULT_SPEED 50000000 155 #define EXYNOS5_SPI_NUM_CONTROLLERS 5 156 #define CONFIG_OF_SPI 157 #endif 158 159 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 160 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 161 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 162 #define CONFIG_ENV_SPI_BUS 1 163 #define CONFIG_ENV_SPI_MAX_HZ 50000000 164 #endif 165 166 /* Ethernet Controllor Driver */ 167 #ifdef CONFIG_CMD_NET 168 #define CONFIG_SMC911X 169 #define CONFIG_SMC911X_BASE 0x5000000 170 #define CONFIG_SMC911X_16_BIT 171 #define CONFIG_ENV_SROM_BANK 1 172 #endif /*CONFIG_CMD_NET*/ 173 174 /* SHA hashing */ 175 #define CONFIG_CMD_HASH 176 #define CONFIG_HASH_VERIFY 177 #define CONFIG_SHA1 178 #define CONFIG_SHA256 179 180 /* Enable Time Command */ 181 #define CONFIG_CMD_TIME 182 183 #define CONFIG_CMD_GPIO 184 185 /* USB boot mode */ 186 #define CONFIG_USB_BOOTING 187 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 188 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 189 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 190 191 /* Enable FIT support and comparison */ 192 #define CONFIG_FIT 193 #define CONFIG_FIT_BEST_MATCH 194 195 #endif /* __CONFIG_EXYNOS5_COMMON_H */ 196