1 /* 2 * Copyright (C) 2013 Samsung Electronics 3 * 4 * Configuration settings for the SAMSUNG EXYNOS5 board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_EXYNOS5_COMMON_H 10 #define __CONFIG_EXYNOS5_COMMON_H 11 12 /* High Level Configuration Options */ 13 #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 14 #define CONFIG_S5P /* S5P Family */ 15 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ 16 17 #include <asm/arch/cpu.h> /* get chip and board defs */ 18 19 #define CONFIG_SYS_GENERIC_BOARD 20 #define CONFIG_ARCH_CPU_INIT 21 #define CONFIG_DISPLAY_CPUINFO 22 #define CONFIG_DISPLAY_BOARDINFO 23 #define CONFIG_BOARD_COMMON 24 #define CONFIG_ARCH_EARLY_INIT_R 25 #define CONFIG_EXYNOS_SPL 26 27 /* Allow tracing to be enabled */ 28 #define CONFIG_TRACE 29 #define CONFIG_CMD_TRACE 30 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 31 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 32 #define CONFIG_TRACE_EARLY 33 #define CONFIG_TRACE_EARLY_ADDR 0x50000000 34 35 /* Keep L2 Cache Disabled */ 36 #define CONFIG_SYS_CACHELINE_SIZE 64 37 #define CONFIG_CMD_CACHE 38 39 /* Enable ACE acceleration for SHA1 and SHA256 */ 40 #define CONFIG_EXYNOS_ACE_SHA 41 #define CONFIG_SHA_HW_ACCEL 42 43 /* input clock of PLL: SMDK5250 has 24MHz input clock */ 44 #define CONFIG_SYS_CLK_FREQ 24000000 45 46 #define CONFIG_SETUP_MEMORY_TAGS 47 #define CONFIG_CMDLINE_TAG 48 #define CONFIG_INITRD_TAG 49 #define CONFIG_CMDLINE_EDITING 50 51 /* Power Down Modes */ 52 #define S5P_CHECK_SLEEP 0x00000BAD 53 #define S5P_CHECK_DIDLE 0xBAD00000 54 #define S5P_CHECK_LPA 0xABAD0000 55 56 /* Offset for inform registers */ 57 #define INFORM0_OFFSET 0x800 58 #define INFORM1_OFFSET 0x804 59 #define INFORM2_OFFSET 0x808 60 #define INFORM3_OFFSET 0x80c 61 62 /* Size of malloc() pool */ 63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) 64 65 /* select serial console configuration */ 66 #define CONFIG_BAUDRATE 115200 67 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 68 #define CONFIG_SILENT_CONSOLE 69 70 /* Enable keyboard */ 71 #define CONFIG_CROS_EC /* CROS_EC protocol */ 72 #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ 73 #define CONFIG_CMD_CROS_EC 74 #define CONFIG_KEYBOARD 75 76 /* Console configuration */ 77 #define CONFIG_CONSOLE_MUX 78 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 79 #define EXYNOS_DEVICE_SETTINGS \ 80 "stdin=serial,cros-ec-keyb\0" \ 81 "stdout=serial,lcd\0" \ 82 "stderr=serial,lcd\0" 83 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 EXYNOS_DEVICE_SETTINGS 86 87 /* SD/MMC configuration */ 88 #define CONFIG_GENERIC_MMC 89 #define CONFIG_MMC 90 #define CONFIG_SDHCI 91 #define CONFIG_S5P_SDHCI 92 #define CONFIG_DWMMC 93 #define CONFIG_EXYNOS_DWMMC 94 #define CONFIG_SUPPORT_EMMC_BOOT 95 #define CONFIG_BOUNCE_BUFFER 96 97 #define CONFIG_BOARD_EARLY_INIT_F 98 #define CONFIG_SKIP_LOWLEVEL_INIT 99 100 /* PWM */ 101 #define CONFIG_PWM 102 103 /* allow to overwrite serial and ethaddr */ 104 #define CONFIG_ENV_OVERWRITE 105 106 /* Command definition*/ 107 #include <config_cmd_default.h> 108 109 #define CONFIG_CMD_PING 110 #define CONFIG_CMD_ELF 111 #define CONFIG_CMD_MMC 112 #define CONFIG_CMD_EXT2 113 #define CONFIG_CMD_FAT 114 #define CONFIG_CMD_NET 115 #define CONFIG_CMD_HASH 116 117 #define CONFIG_BOOTDELAY 3 118 #define CONFIG_ZERO_BOOTDELAY_CHECK 119 120 /* Thermal Management Unit */ 121 #define CONFIG_EXYNOS_TMU 122 #define CONFIG_CMD_DTT 123 #define CONFIG_TMU_CMD_DTT 124 125 /* TPM */ 126 #define CONFIG_TPM 127 #define CONFIG_CMD_TPM 128 #define CONFIG_TPM_TIS_I2C 129 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 130 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 131 132 /* MMC SPL */ 133 #define COPY_BL2_FNPTR_ADDR 0x02020030 134 135 #define CONFIG_SPL_LIBCOMMON_SUPPORT 136 #define CONFIG_SPL_GPIO_SUPPORT 137 138 /* specific .lds file */ 139 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 140 141 /* Miscellaneous configurable options */ 142 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 143 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 144 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 145 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ 146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 147 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" 148 /* Boot Argument Buffer Size */ 149 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 150 /* memtest works on */ 151 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 152 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 153 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 154 155 #define CONFIG_RD_LVL 156 157 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 158 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 159 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 160 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 161 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 162 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 163 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 164 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 165 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 166 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 167 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 168 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 169 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 170 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 171 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 172 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 173 174 #define CONFIG_SYS_MONITOR_BASE 0x00000000 175 176 /* FLASH and environment organization */ 177 #define CONFIG_SYS_NO_FLASH 178 #undef CONFIG_CMD_IMLS 179 180 #define CONFIG_SYS_MMC_ENV_DEV 0 181 182 #define CONFIG_SECURE_BL1_ONLY 183 184 /* Secure FW size configuration */ 185 #ifdef CONFIG_SECURE_BL1_ONLY 186 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 187 #else 188 #define CONFIG_SEC_FW_SIZE 0 189 #endif 190 191 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 192 #define CONFIG_RES_BLOCK_SIZE (512) 193 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 194 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 195 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 196 197 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 198 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 199 200 /* Store environment at the end of a 4 MB SPI flash */ 201 #define FLASH_SIZE (0x4 << 20) 202 #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) 203 204 /* U-boot copy size from boot Media to DRAM.*/ 205 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 206 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 207 208 #define CONFIG_SPI_BOOTING 209 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 210 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) 211 212 #define CONFIG_DOS_PARTITION 213 #define CONFIG_EFI_PARTITION 214 #define CONFIG_CMD_PART 215 #define CONFIG_PARTITION_UUIDS 216 217 /* I2C */ 218 #define CONFIG_SYS_I2C_INIT_BOARD 219 #define CONFIG_SYS_I2C 220 #define CONFIG_CMD_I2C 221 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ 222 #define CONFIG_SYS_I2C_S3C24X0 223 #define CONFIG_I2C_MULTI_BUS 224 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 225 #define CONFIG_I2C_EDID 226 227 /* SPI */ 228 #define CONFIG_ENV_IS_IN_SPI_FLASH 229 #define CONFIG_SPI_FLASH 230 #define CONFIG_ENV_SPI_BASE 0x12D30000 231 232 #ifdef CONFIG_SPI_FLASH 233 #define CONFIG_EXYNOS_SPI 234 #define CONFIG_CMD_SF 235 #define CONFIG_CMD_SPI 236 #define CONFIG_SPI_FLASH_WINBOND 237 #define CONFIG_SPI_FLASH_GIGADEVICE 238 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 239 #define CONFIG_SF_DEFAULT_SPEED 50000000 240 #define EXYNOS5_SPI_NUM_CONTROLLERS 5 241 #define CONFIG_OF_SPI 242 #endif 243 244 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 245 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 246 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 247 #define CONFIG_ENV_SPI_BUS 1 248 #define CONFIG_ENV_SPI_MAX_HZ 50000000 249 #endif 250 251 /* PMIC */ 252 #define CONFIG_POWER 253 #define CONFIG_POWER_I2C 254 #define CONFIG_POWER_TPS65090 255 256 /* Ethernet Controllor Driver */ 257 #ifdef CONFIG_CMD_NET 258 #define CONFIG_SMC911X 259 #define CONFIG_SMC911X_BASE 0x5000000 260 #define CONFIG_SMC911X_16_BIT 261 #define CONFIG_ENV_SROM_BANK 1 262 #endif /*CONFIG_CMD_NET*/ 263 264 /* Enable PXE Support */ 265 #ifdef CONFIG_CMD_NET 266 #define CONFIG_CMD_PXE 267 #define CONFIG_MENU 268 #endif 269 270 /* Enable devicetree support */ 271 #define CONFIG_OF_LIBFDT 272 273 /* SHA hashing */ 274 #define CONFIG_CMD_HASH 275 #define CONFIG_HASH_VERIFY 276 #define CONFIG_SHA1 277 #define CONFIG_SHA256 278 279 /* Enable Time Command */ 280 #define CONFIG_CMD_TIME 281 282 #define CONFIG_CMD_BOOTZ 283 284 #define CONFIG_CMD_GPIO 285 286 /* USB boot mode */ 287 #define CONFIG_USB_BOOTING 288 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 289 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 290 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 291 292 #endif /* __CONFIG_EXYNOS5_COMMON_H */ 293