xref: /rk3399_rockchip-uboot/include/configs/embestmx6boards.h (revision f8cb101e1e3f5ee2007b78b6b12e24120385aeac)
13cbeb0f0SEric Benard /*
23cbeb0f0SEric Benard  * Copyright (C) 2014 Eukréa Electromatique
33cbeb0f0SEric Benard  * Author: Eric Bénard <eric@eukrea.com>
43cbeb0f0SEric Benard  *
53cbeb0f0SEric Benard  * Configuration settings for the Embest RIoTboard
63cbeb0f0SEric Benard  *
73cbeb0f0SEric Benard  * based on mx6*sabre*.h which are :
83cbeb0f0SEric Benard  * Copyright (C) 2012 Freescale Semiconductor, Inc.
93cbeb0f0SEric Benard  *
103cbeb0f0SEric Benard  * SPDX-License-Identifier:	GPL-2.0+
113cbeb0f0SEric Benard  */
123cbeb0f0SEric Benard 
133cbeb0f0SEric Benard #ifndef __RIOTBOARD_CONFIG_H
143cbeb0f0SEric Benard #define __RIOTBOARD_CONFIG_H
153cbeb0f0SEric Benard 
163cbeb0f0SEric Benard #include <asm/arch/imx-regs.h>
173cbeb0f0SEric Benard #include <asm/imx-common/gpio.h>
183cbeb0f0SEric Benard 
193cbeb0f0SEric Benard #include "mx6_common.h"
203cbeb0f0SEric Benard #include <linux/sizes.h>
213cbeb0f0SEric Benard 
226ed9c7bbSIain Paton #define CONFIG_SYS_GENERIC_BOARD
236ed9c7bbSIain Paton 
243cbeb0f0SEric Benard #define CONFIG_MXC_UART_BASE		UART2_BASE
25fa4a7a43SFabio Estevam #define CONFIG_CONSOLE_DEV		"ttymxc1"
263cbeb0f0SEric Benard #define CONFIG_MMCROOT			"/dev/mmcblk1p2"
273cbeb0f0SEric Benard 
283cbeb0f0SEric Benard #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
293cbeb0f0SEric Benard 
303cbeb0f0SEric Benard #define CONFIG_MX6
313cbeb0f0SEric Benard 
323cbeb0f0SEric Benard #define CONFIG_DISPLAY_CPUINFO
333cbeb0f0SEric Benard #define CONFIG_DISPLAY_BOARDINFO
343cbeb0f0SEric Benard 
353cbeb0f0SEric Benard #define CONFIG_CMDLINE_TAG
363cbeb0f0SEric Benard #define CONFIG_SETUP_MEMORY_TAGS
373cbeb0f0SEric Benard #define CONFIG_INITRD_TAG
383cbeb0f0SEric Benard #define CONFIG_REVISION_TAG
393cbeb0f0SEric Benard 
403cbeb0f0SEric Benard /* Size of malloc() pool */
413cbeb0f0SEric Benard #define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
423cbeb0f0SEric Benard 
433cbeb0f0SEric Benard #define CONFIG_BOARD_EARLY_INIT_F
443cbeb0f0SEric Benard #define CONFIG_BOARD_LATE_INIT
453cbeb0f0SEric Benard #define CONFIG_MXC_GPIO
463cbeb0f0SEric Benard 
473cbeb0f0SEric Benard #define CONFIG_MXC_UART
483cbeb0f0SEric Benard 
493cbeb0f0SEric Benard #define CONFIG_CMD_FUSE
503cbeb0f0SEric Benard #ifdef CONFIG_CMD_FUSE
513cbeb0f0SEric Benard #define CONFIG_MXC_OCOTP
523cbeb0f0SEric Benard #endif
533cbeb0f0SEric Benard 
543cbeb0f0SEric Benard /* I2C Configs */
553cbeb0f0SEric Benard #define CONFIG_CMD_I2C
563cbeb0f0SEric Benard #define CONFIG_SYS_I2C
573cbeb0f0SEric Benard #define CONFIG_SYS_I2C_MXC
58*f8cb101eSYork Sun #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
593cbeb0f0SEric Benard #define CONFIG_SYS_I2C_SPEED		100000
603cbeb0f0SEric Benard 
613cbeb0f0SEric Benard /* USB Configs */
623cbeb0f0SEric Benard #define CONFIG_CMD_USB
633cbeb0f0SEric Benard #define CONFIG_USB_EHCI
643cbeb0f0SEric Benard #define CONFIG_USB_EHCI_MX6
653cbeb0f0SEric Benard #define CONFIG_USB_STORAGE
663cbeb0f0SEric Benard #define CONFIG_USB_HOST_ETHER
673cbeb0f0SEric Benard #define CONFIG_USB_ETHER_ASIX
683cbeb0f0SEric Benard #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
693cbeb0f0SEric Benard #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
703cbeb0f0SEric Benard #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
713cbeb0f0SEric Benard #define CONFIG_MXC_USB_FLAGS	0
723cbeb0f0SEric Benard 
733cbeb0f0SEric Benard /* MMC Configs */
743cbeb0f0SEric Benard #define CONFIG_FSL_ESDHC
753cbeb0f0SEric Benard #define CONFIG_FSL_USDHC
763cbeb0f0SEric Benard #define CONFIG_SYS_FSL_ESDHC_ADDR      0
773cbeb0f0SEric Benard 
783cbeb0f0SEric Benard #define CONFIG_MMC
793cbeb0f0SEric Benard #define CONFIG_CMD_MMC
803cbeb0f0SEric Benard #define CONFIG_GENERIC_MMC
813cbeb0f0SEric Benard #define CONFIG_BOUNCE_BUFFER
823cbeb0f0SEric Benard 
833cbeb0f0SEric Benard #define CONFIG_FEC_MXC
843cbeb0f0SEric Benard #define CONFIG_MII
853cbeb0f0SEric Benard #define IMX_FEC_BASE			ENET_BASE_ADDR
863cbeb0f0SEric Benard #define CONFIG_FEC_XCV_TYPE		RGMII
873cbeb0f0SEric Benard #define CONFIG_ETHPRIME			"FEC"
883cbeb0f0SEric Benard #define CONFIG_FEC_MXC_PHYADDR		4
893cbeb0f0SEric Benard 
903cbeb0f0SEric Benard #define CONFIG_PHYLIB
913cbeb0f0SEric Benard #define CONFIG_PHY_ATHEROS
923cbeb0f0SEric Benard 
933cbeb0f0SEric Benard #define CONFIG_CMD_SF
943cbeb0f0SEric Benard #ifdef CONFIG_CMD_SF
953cbeb0f0SEric Benard #define CONFIG_SPI_FLASH
963cbeb0f0SEric Benard #define CONFIG_SPI_FLASH_SST
973cbeb0f0SEric Benard #define CONFIG_MXC_SPI
983cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_BUS		0
99155fa9afSNikita Kiryanov #define CONFIG_SF_DEFAULT_CS		0
1003cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_SPEED		20000000
1013cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
1023cbeb0f0SEric Benard #endif
1033cbeb0f0SEric Benard 
1043cbeb0f0SEric Benard /* allow to overwrite serial and ethaddr */
1053cbeb0f0SEric Benard #define CONFIG_ENV_OVERWRITE
1063cbeb0f0SEric Benard #define CONFIG_CONS_INDEX              1
1073cbeb0f0SEric Benard #define CONFIG_BAUDRATE                        115200
1083cbeb0f0SEric Benard 
1093cbeb0f0SEric Benard /* Command definition */
1103cbeb0f0SEric Benard #include <config_cmd_default.h>
111729d2a34SIain Paton #undef CONFIG_CMD_FPGA
1123cbeb0f0SEric Benard 
1133cbeb0f0SEric Benard #define CONFIG_CMD_BMODE
1143cbeb0f0SEric Benard #define CONFIG_CMD_SETEXPR
1153cbeb0f0SEric Benard #undef CONFIG_CMD_IMLS
1163cbeb0f0SEric Benard 
1173cbeb0f0SEric Benard #define CONFIG_LOADADDR                        0x12000000
1183cbeb0f0SEric Benard #define CONFIG_SYS_TEXT_BASE           0x17800000
1193cbeb0f0SEric Benard 
1203cbeb0f0SEric Benard #define CONFIG_ARP_TIMEOUT     200UL
1213cbeb0f0SEric Benard 
1223cbeb0f0SEric Benard /* Miscellaneous configurable options */
1233cbeb0f0SEric Benard #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
1243cbeb0f0SEric Benard #define CONFIG_SYS_CBSIZE              256
1253cbeb0f0SEric Benard 
1263cbeb0f0SEric Benard /* Print Buffer Size */
1273cbeb0f0SEric Benard #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1283cbeb0f0SEric Benard #define CONFIG_SYS_MAXARGS             16
1293cbeb0f0SEric Benard #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
1303cbeb0f0SEric Benard 
1313cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_START       0x10000000
1323cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_END         0x10010000
1333cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
1343cbeb0f0SEric Benard 
1353cbeb0f0SEric Benard #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
1363cbeb0f0SEric Benard 
1373cbeb0f0SEric Benard #define CONFIG_STACKSIZE               (128 * 1024)
1383cbeb0f0SEric Benard 
1393cbeb0f0SEric Benard /* Physical Memory Map */
1403cbeb0f0SEric Benard #define CONFIG_NR_DRAM_BANKS           1
1413cbeb0f0SEric Benard #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
1423cbeb0f0SEric Benard 
1433cbeb0f0SEric Benard #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
1443cbeb0f0SEric Benard #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
1453cbeb0f0SEric Benard #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
1463cbeb0f0SEric Benard 
1473cbeb0f0SEric Benard #define CONFIG_SYS_INIT_SP_OFFSET \
1483cbeb0f0SEric Benard 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1493cbeb0f0SEric Benard #define CONFIG_SYS_INIT_SP_ADDR \
1503cbeb0f0SEric Benard 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
1513cbeb0f0SEric Benard 
1523cbeb0f0SEric Benard /* FLASH and environment organization */
1533cbeb0f0SEric Benard #define CONFIG_SYS_NO_FLASH
1543cbeb0f0SEric Benard 
1553cbeb0f0SEric Benard #define CONFIG_ENV_SIZE			(8 * 1024)
1563cbeb0f0SEric Benard 
1573cbeb0f0SEric Benard #if defined(CONFIG_ENV_IS_IN_MMC)
1583cbeb0f0SEric Benard /* RiOTboard */
159c86efd85SIain Paton #define CONFIG_FDTFILE	"imx6dl-riotboard.dtb"
1603cbeb0f0SEric Benard #define CONFIG_SYS_FSL_USDHC_NUM	3
1613cbeb0f0SEric Benard #define CONFIG_SYS_MMC_ENV_DEV		2	/* SDHC4 */
1623cbeb0f0SEric Benard #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
1633cbeb0f0SEric Benard #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
1643cbeb0f0SEric Benard #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
1653cbeb0f0SEric Benard /* MarSBoard */
166c86efd85SIain Paton #define CONFIG_FDTFILE	"imx6q-marsboard.dtb"
1673cbeb0f0SEric Benard #define CONFIG_SYS_FSL_USDHC_NUM	2
1683cbeb0f0SEric Benard #define CONFIG_ENV_OFFSET		(768 * 1024)
1693cbeb0f0SEric Benard #define CONFIG_ENV_SECT_SIZE		(8 * 1024)
1703cbeb0f0SEric Benard #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
1713cbeb0f0SEric Benard #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
1723cbeb0f0SEric Benard #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
1733cbeb0f0SEric Benard #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
1743cbeb0f0SEric Benard #endif
1753cbeb0f0SEric Benard 
1763cbeb0f0SEric Benard #ifndef CONFIG_SYS_DCACHE_OFF
1773cbeb0f0SEric Benard #define CONFIG_CMD_CACHE
1783cbeb0f0SEric Benard #endif
1793cbeb0f0SEric Benard 
1803cbeb0f0SEric Benard /* Framebuffer */
1813cbeb0f0SEric Benard #define CONFIG_VIDEO
1823cbeb0f0SEric Benard #define CONFIG_VIDEO_IPUV3
1833cbeb0f0SEric Benard #define CONFIG_CFB_CONSOLE
1843cbeb0f0SEric Benard #define CONFIG_VGA_AS_SINGLE_DEVICE
1853cbeb0f0SEric Benard #define CONFIG_SYS_CONSOLE_IS_IN_ENV
1863cbeb0f0SEric Benard #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
1873cbeb0f0SEric Benard #define CONFIG_VIDEO_BMP_RLE8
1883cbeb0f0SEric Benard #define CONFIG_SPLASH_SCREEN
1893cbeb0f0SEric Benard #define CONFIG_SPLASH_SCREEN_ALIGN
1903cbeb0f0SEric Benard #define CONFIG_BMP_16BPP
1913cbeb0f0SEric Benard #define CONFIG_VIDEO_LOGO
1923cbeb0f0SEric Benard #define CONFIG_VIDEO_BMP_LOGO
1933cbeb0f0SEric Benard #define CONFIG_IPUV3_CLK 260000000
1943cbeb0f0SEric Benard #define CONFIG_IMX_HDMI
1953cbeb0f0SEric Benard #define CONFIG_IMX_VIDEO_SKIP
1963cbeb0f0SEric Benard 
197729d2a34SIain Paton #include <config_distro_defaults.h>
198729d2a34SIain Paton 
199c86efd85SIain Paton /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
200c86efd85SIain Paton  * 1M script, 1M pxe and the ramdisk at the end */
201c86efd85SIain Paton #define MEM_LAYOUT_ENV_SETTINGS \
202c86efd85SIain Paton 	"bootm_size=0x10000000\0" \
203c86efd85SIain Paton 	"kernel_addr_r=0x12000000\0" \
204c86efd85SIain Paton 	"fdt_addr_r=0x13000000\0" \
205c86efd85SIain Paton 	"scriptaddr=0x13100000\0" \
206c86efd85SIain Paton 	"pxefile_addr_r=0x13200000\0" \
207c86efd85SIain Paton 	"ramdisk_addr_r=0x13300000\0"
208c86efd85SIain Paton 
209c86efd85SIain Paton #define BOOT_TARGET_DEVICES(func) \
210c86efd85SIain Paton 	func(MMC, mmc, 0) \
211c86efd85SIain Paton 	func(MMC, mmc, 1) \
212c86efd85SIain Paton 	func(MMC, mmc, 2) \
213c86efd85SIain Paton 	func(USB, usb, 0) \
214c86efd85SIain Paton 	func(PXE, pxe, na) \
215c86efd85SIain Paton 	func(DHCP, dhcp, na)
216c86efd85SIain Paton 
217c86efd85SIain Paton #include <config_distro_bootcmd.h>
218c86efd85SIain Paton 
219c86efd85SIain Paton #define CONSOLE_STDIN_SETTINGS \
220c86efd85SIain Paton 	"stdin=serial\0"
221c86efd85SIain Paton 
222c86efd85SIain Paton #define CONSOLE_STDOUT_SETTINGS \
223c86efd85SIain Paton 	"stdout=serial\0" \
224c86efd85SIain Paton 	"stderr=serial\0"
225c86efd85SIain Paton 
226c86efd85SIain Paton #define CONSOLE_ENV_SETTINGS \
227c86efd85SIain Paton 	CONSOLE_STDIN_SETTINGS \
228c86efd85SIain Paton 	CONSOLE_STDOUT_SETTINGS
229c86efd85SIain Paton 
230c86efd85SIain Paton #define CONFIG_EXTRA_ENV_SETTINGS \
231c86efd85SIain Paton 	CONSOLE_ENV_SETTINGS \
232c86efd85SIain Paton 	MEM_LAYOUT_ENV_SETTINGS \
233c86efd85SIain Paton 	"fdtfile=" CONFIG_FDTFILE "\0" \
234c86efd85SIain Paton 	BOOTENV
235c86efd85SIain Paton 
2363cbeb0f0SEric Benard #endif                         /* __RIOTBOARD_CONFIG_H */
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