13cbeb0f0SEric Benard /* 23cbeb0f0SEric Benard * Copyright (C) 2014 Eukréa Electromatique 33cbeb0f0SEric Benard * Author: Eric Bénard <eric@eukrea.com> 43cbeb0f0SEric Benard * 53cbeb0f0SEric Benard * Configuration settings for the Embest RIoTboard 63cbeb0f0SEric Benard * 73cbeb0f0SEric Benard * based on mx6*sabre*.h which are : 83cbeb0f0SEric Benard * Copyright (C) 2012 Freescale Semiconductor, Inc. 93cbeb0f0SEric Benard * 103cbeb0f0SEric Benard * SPDX-License-Identifier: GPL-2.0+ 113cbeb0f0SEric Benard */ 123cbeb0f0SEric Benard 133cbeb0f0SEric Benard #ifndef __RIOTBOARD_CONFIG_H 143cbeb0f0SEric Benard #define __RIOTBOARD_CONFIG_H 153cbeb0f0SEric Benard 163cbeb0f0SEric Benard #define CONFIG_MXC_UART_BASE UART2_BASE 1712ca05a3SSimon Glass #define CONSOLE_DEV "ttymxc1" 183cbeb0f0SEric Benard 193cbeb0f0SEric Benard #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 203cbeb0f0SEric Benard 211368f993SAdrian Alonso #define CONFIG_IMX_THERMAL 223cbeb0f0SEric Benard 233cbeb0f0SEric Benard /* Size of malloc() pool */ 243cbeb0f0SEric Benard #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 253cbeb0f0SEric Benard 263cbeb0f0SEric Benard #define CONFIG_MXC_UART 273cbeb0f0SEric Benard 283cbeb0f0SEric Benard /* I2C Configs */ 293cbeb0f0SEric Benard #define CONFIG_SYS_I2C 303cbeb0f0SEric Benard #define CONFIG_SYS_I2C_MXC 3103544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 3203544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 33f8cb101eSYork Sun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 343cbeb0f0SEric Benard #define CONFIG_SYS_I2C_SPEED 100000 353cbeb0f0SEric Benard 363cbeb0f0SEric Benard /* USB Configs */ 373cbeb0f0SEric Benard #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 383cbeb0f0SEric Benard #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 393cbeb0f0SEric Benard #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 403cbeb0f0SEric Benard #define CONFIG_MXC_USB_FLAGS 0 413cbeb0f0SEric Benard 423cbeb0f0SEric Benard /* MMC Configs */ 433cbeb0f0SEric Benard #define CONFIG_SYS_FSL_ESDHC_ADDR 0 443cbeb0f0SEric Benard 453cbeb0f0SEric Benard #define CONFIG_FEC_MXC 463cbeb0f0SEric Benard #define CONFIG_MII 473cbeb0f0SEric Benard #define IMX_FEC_BASE ENET_BASE_ADDR 483cbeb0f0SEric Benard #define CONFIG_FEC_XCV_TYPE RGMII 493cbeb0f0SEric Benard #define CONFIG_ETHPRIME "FEC" 503cbeb0f0SEric Benard #define CONFIG_FEC_MXC_PHYADDR 4 513cbeb0f0SEric Benard 523cbeb0f0SEric Benard #define CONFIG_PHY_ATHEROS 533cbeb0f0SEric Benard 543cbeb0f0SEric Benard #ifdef CONFIG_CMD_SF 553cbeb0f0SEric Benard #define CONFIG_MXC_SPI 563cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_BUS 0 57155fa9afSNikita Kiryanov #define CONFIG_SF_DEFAULT_CS 0 583cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_SPEED 20000000 593cbeb0f0SEric Benard #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 603cbeb0f0SEric Benard #endif 613cbeb0f0SEric Benard 623cbeb0f0SEric Benard #define CONFIG_ARP_TIMEOUT 200UL 633cbeb0f0SEric Benard 643cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_START 0x10000000 653cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_END 0x10010000 663cbeb0f0SEric Benard #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 673cbeb0f0SEric Benard 683cbeb0f0SEric Benard /* Physical Memory Map */ 693cbeb0f0SEric Benard #define CONFIG_NR_DRAM_BANKS 1 703cbeb0f0SEric Benard #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 713cbeb0f0SEric Benard 723cbeb0f0SEric Benard #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 733cbeb0f0SEric Benard #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 743cbeb0f0SEric Benard #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 753cbeb0f0SEric Benard 763cbeb0f0SEric Benard #define CONFIG_SYS_INIT_SP_OFFSET \ 773cbeb0f0SEric Benard (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 783cbeb0f0SEric Benard #define CONFIG_SYS_INIT_SP_ADDR \ 793cbeb0f0SEric Benard (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 803cbeb0f0SEric Benard 81056845c2SPeter Robinson /* Environment organization */ 823cbeb0f0SEric Benard #define CONFIG_ENV_SIZE (8 * 1024) 833cbeb0f0SEric Benard 843cbeb0f0SEric Benard #if defined(CONFIG_ENV_IS_IN_MMC) 853cbeb0f0SEric Benard /* RiOTboard */ 86c86efd85SIain Paton #define CONFIG_FDTFILE "imx6dl-riotboard.dtb" 873cbeb0f0SEric Benard #define CONFIG_SYS_FSL_USDHC_NUM 3 883cbeb0f0SEric Benard #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ 893cbeb0f0SEric Benard #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 903cbeb0f0SEric Benard #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 913cbeb0f0SEric Benard #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) 923cbeb0f0SEric Benard /* MarSBoard */ 93c86efd85SIain Paton #define CONFIG_FDTFILE "imx6q-marsboard.dtb" 943cbeb0f0SEric Benard #define CONFIG_SYS_FSL_USDHC_NUM 2 953cbeb0f0SEric Benard #define CONFIG_ENV_OFFSET (768 * 1024) 963cbeb0f0SEric Benard #define CONFIG_ENV_SECT_SIZE (8 * 1024) 973cbeb0f0SEric Benard #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 983cbeb0f0SEric Benard #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 993cbeb0f0SEric Benard #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 1003cbeb0f0SEric Benard #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 1013cbeb0f0SEric Benard #endif 1023cbeb0f0SEric Benard 1033cbeb0f0SEric Benard /* Framebuffer */ 1043cbeb0f0SEric Benard #define CONFIG_VIDEO_IPUV3 1053cbeb0f0SEric Benard #define CONFIG_VIDEO_BMP_RLE8 1063cbeb0f0SEric Benard #define CONFIG_SPLASH_SCREEN 1073cbeb0f0SEric Benard #define CONFIG_SPLASH_SCREEN_ALIGN 1083cbeb0f0SEric Benard #define CONFIG_BMP_16BPP 1093cbeb0f0SEric Benard #define CONFIG_VIDEO_LOGO 1103cbeb0f0SEric Benard #define CONFIG_VIDEO_BMP_LOGO 1113cbeb0f0SEric Benard #define CONFIG_IPUV3_CLK 260000000 1123cbeb0f0SEric Benard #define CONFIG_IMX_HDMI 1133cbeb0f0SEric Benard #define CONFIG_IMX_VIDEO_SKIP 1143cbeb0f0SEric Benard 115729d2a34SIain Paton #include <config_distro_defaults.h> 116e51c1e8eSPeter Robinson #include "mx6_common.h" 117729d2a34SIain Paton 118c86efd85SIain Paton /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, 119c86efd85SIain Paton * 1M script, 1M pxe and the ramdisk at the end */ 120c86efd85SIain Paton #define MEM_LAYOUT_ENV_SETTINGS \ 121c86efd85SIain Paton "bootm_size=0x10000000\0" \ 122c86efd85SIain Paton "kernel_addr_r=0x12000000\0" \ 123c86efd85SIain Paton "fdt_addr_r=0x13000000\0" \ 124c86efd85SIain Paton "scriptaddr=0x13100000\0" \ 125c86efd85SIain Paton "pxefile_addr_r=0x13200000\0" \ 126c86efd85SIain Paton "ramdisk_addr_r=0x13300000\0" 127c86efd85SIain Paton 128c86efd85SIain Paton #define BOOT_TARGET_DEVICES(func) \ 129c86efd85SIain Paton func(MMC, mmc, 0) \ 130c86efd85SIain Paton func(MMC, mmc, 1) \ 131c86efd85SIain Paton func(MMC, mmc, 2) \ 132c86efd85SIain Paton func(USB, usb, 0) \ 133c86efd85SIain Paton func(PXE, pxe, na) \ 134c86efd85SIain Paton func(DHCP, dhcp, na) 135c86efd85SIain Paton 136*0f29a61cSFabio Berton #define CONFIG_BOOTCOMMAND \ 137*0f29a61cSFabio Berton "run finduuid; " \ 138*0f29a61cSFabio Berton "run distro_bootcmd" 139*0f29a61cSFabio Berton 140c86efd85SIain Paton #include <config_distro_bootcmd.h> 141c86efd85SIain Paton 142c86efd85SIain Paton #define CONSOLE_STDIN_SETTINGS \ 143c86efd85SIain Paton "stdin=serial\0" 144c86efd85SIain Paton 145c86efd85SIain Paton #define CONSOLE_STDOUT_SETTINGS \ 146c86efd85SIain Paton "stdout=serial\0" \ 147c86efd85SIain Paton "stderr=serial\0" 148c86efd85SIain Paton 149c86efd85SIain Paton #define CONSOLE_ENV_SETTINGS \ 150c86efd85SIain Paton CONSOLE_STDIN_SETTINGS \ 151c86efd85SIain Paton CONSOLE_STDOUT_SETTINGS 152c86efd85SIain Paton 153c86efd85SIain Paton #define CONFIG_EXTRA_ENV_SETTINGS \ 154c86efd85SIain Paton CONSOLE_ENV_SETTINGS \ 155c86efd85SIain Paton MEM_LAYOUT_ENV_SETTINGS \ 156c86efd85SIain Paton "fdtfile=" CONFIG_FDTFILE "\0" \ 157*0f29a61cSFabio Berton "finduuid=part uuid mmc 0:1 uuid\0" \ 158c86efd85SIain Paton BOOTENV 159c86efd85SIain Paton 1603cbeb0f0SEric Benard #endif /* __RIOTBOARD_CONFIG_H */ 161