1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_SERIAL_SUPPORT 21 #define CONFIG_SPL_TEXT_BASE 0xffff0000 22 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 23 #define CONFIG_SPL_STACK 0x00020000 24 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 25 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 26 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 27 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 28 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 29 #define CONFIG_SPL_BOARD_INIT 30 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 31 #define CONFIG_SYS_UBOOT_START 0x00800000 32 #define CONFIG_SYS_TEXT_BASE 0x00800000 33 34 /* 35 * Version number information 36 */ 37 38 #define CONFIG_IDENT_STRING " EDMiniV2" 39 40 /* 41 * High Level Configuration Options (easy to change) 42 */ 43 44 #define CONFIG_MARVELL 1 45 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 46 #define CONFIG_88F5182 1 /* SOC Name */ 47 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 48 49 #include <asm/arch/orion5x.h> 50 /* 51 * CLKs configurations 52 */ 53 54 /* 55 * Board-specific values for Orion5x MPP low level init: 56 * - MPPs 12 to 15 are SATA LEDs (mode 5) 57 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 58 * MPP16 to MPP19, mode 0 for others 59 */ 60 61 #define ORION5X_MPP0_7 0x00000003 62 #define ORION5X_MPP8_15 0x55550000 63 #define ORION5X_MPP16_23 0x00005555 64 65 /* 66 * Board-specific values for Orion5x GPIO low level init: 67 * - GPIO3 is input (RTC interrupt) 68 * - GPIO16 is Power LED control (0 = on, 1 = off) 69 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 70 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 71 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 72 * - GPIO22 is SATA disk power status () 73 * - GPIO23 is supply status for SATA disk () 74 * - GPIO24 is supply control for board (write 1 to power off) 75 * Last GPIO is 25, further bits are supposed to be 0. 76 * Enable mask has ones for INPUT, 0 for OUTPUT. 77 * Default is LED ON, board ON :) 78 */ 79 80 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 81 #define ORION5X_GPIO_OUT_VALUE 0x00000000 82 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 83 84 /* 85 * NS16550 Configuration 86 */ 87 88 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 90 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 91 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 92 93 /* 94 * Serial Port configuration 95 * The following definitions let you select what serial you want to use 96 * for your console driver. 97 */ 98 99 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 100 #define CONFIG_BAUDRATE 115200 101 #define CONFIG_SYS_BAUDRATE_TABLE \ 102 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 103 104 /* 105 * FLASH configuration 106 */ 107 108 #define CONFIG_SYS_FLASH_CFI 109 #define CONFIG_FLASH_CFI_DRIVER 110 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 111 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 112 #define CONFIG_SYS_FLASH_BASE 0xfff80000 113 114 /* auto boot */ 115 116 /* 117 * For booting Linux, the board info and command line data 118 * have to be in the first 8 MB of memory, since this is 119 * the maximum mapped by the Linux kernel during initialization. 120 */ 121 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 122 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 123 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 124 125 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 127 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 128 /* 129 * Commands configuration 130 */ 131 #define CONFIG_CMD_IDE 132 133 /* 134 * Network 135 */ 136 137 #ifdef CONFIG_CMD_NET 138 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 139 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 140 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 141 #define CONFIG_PHY_BASE_ADR 0x8 142 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 143 #define CONFIG_NETCONSOLE /* include NetConsole support */ 144 #define CONFIG_MII /* expose smi ove miiphy interface */ 145 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 146 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 147 #endif 148 149 /* 150 * IDE 151 */ 152 #ifdef CONFIG_CMD_IDE 153 #define __io 154 #define CONFIG_IDE_PREINIT 155 #define CONFIG_DOS_PARTITION 156 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 157 #define CONFIG_MVSATA_IDE 158 #define CONFIG_MVSATA_IDE_USE_PORT1 159 /* Needs byte-swapping for ATA data register */ 160 #define CONFIG_IDE_SWAP_IO 161 /* Data, registers and alternate blocks are at the same offset */ 162 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 163 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 164 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 165 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 166 #define CONFIG_SYS_ATA_STRIDE 4 167 /* Controller supports 48-bits LBA addressing */ 168 #define CONFIG_LBA48 169 /* A single bus, a single device */ 170 #define CONFIG_SYS_IDE_MAXBUS 1 171 #define CONFIG_SYS_IDE_MAXDEVICE 1 172 /* ATA registers base is at SATA controller base */ 173 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 174 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 175 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 176 /* end of IDE defines */ 177 #endif /* CMD_IDE */ 178 179 /* 180 * Common USB/EHCI configuration 181 */ 182 #ifdef CONFIG_CMD_USB 183 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 184 #define CONFIG_USB_EHCI_MARVELL 185 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 186 #define CONFIG_DOS_PARTITION 187 #define CONFIG_ISO_PARTITION 188 #define CONFIG_SUPPORT_VFAT 189 #endif /* CONFIG_CMD_USB */ 190 191 /* 192 * I2C related stuff 193 */ 194 #ifdef CONFIG_CMD_I2C 195 #define CONFIG_SYS_I2C 196 #define CONFIG_SYS_I2C_MVTWSI 197 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 198 #define CONFIG_SYS_I2C_SLAVE 0x0 199 #define CONFIG_SYS_I2C_SPEED 100000 200 #endif 201 202 /* 203 * Environment variables configurations 204 */ 205 #define CONFIG_ENV_IS_IN_FLASH 1 206 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 207 #define CONFIG_ENV_SIZE 0x2000 208 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 209 210 /* 211 * Size of malloc() pool 212 */ 213 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 214 215 /* 216 * Other required minimal configurations 217 */ 218 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 219 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 220 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 221 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 222 #define CONFIG_NR_DRAM_BANKS 1 223 224 #define CONFIG_SYS_LOAD_ADDR 0x00800000 225 #define CONFIG_SYS_MEMTEST_START 0x00400000 226 #define CONFIG_SYS_MEMTEST_END 0x007fffff 227 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 228 #define CONFIG_SYS_MAXARGS 16 229 230 /* Enable command line editing */ 231 #define CONFIG_CMDLINE_EDITING 232 233 /* provide extensive help */ 234 #define CONFIG_SYS_LONGHELP 235 236 /* additions for new relocation code, must be added to all boards */ 237 #define CONFIG_SYS_SDRAM_BASE 0 238 #define CONFIG_SYS_INIT_SP_ADDR \ 239 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 240 241 #endif /* _CONFIG_EDMINIV2_H */ 242