1 /* 2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 3 * 4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _CONFIG_EB_CPU5282_H_ 10 #define _CONFIG_EB_CPU5282_H_ 11 12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 13 14 /*----------------------------------------------------------------------* 15 * High Level Configuration Options (easy to change) * 16 *----------------------------------------------------------------------*/ 17 18 #define CONFIG_MISC_INIT_R 19 20 #define CONFIG_MCFUART 21 #define CONFIG_SYS_UART_PORT (0) 22 23 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 24 25 #define CONFIG_BOOTCOMMAND "printenv" 26 27 /*----------------------------------------------------------------------* 28 * Options * 29 *----------------------------------------------------------------------*/ 30 31 #define CONFIG_BOOT_RETRY_TIME -1 32 #define CONFIG_RESET_TO_RETRY 33 #define CONFIG_SPLASH_SCREEN 34 35 #define CONFIG_HW_WATCHDOG 36 37 #define STATUS_LED_ACTIVE 0 38 39 /*----------------------------------------------------------------------* 40 * Configuration for environment * 41 * Environment is in the second sector of the first 256k of flash * 42 *----------------------------------------------------------------------*/ 43 44 #define CONFIG_ENV_ADDR 0xFF040000 45 #define CONFIG_ENV_SECT_SIZE 0x00020000 46 47 /* 48 * BOOTP options 49 */ 50 #define CONFIG_BOOTP_BOOTFILESIZE 51 #define CONFIG_BOOTP_BOOTPATH 52 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_HOSTNAME 54 55 /* 56 * Command line configuration. 57 */ 58 #define CONFIG_CMDLINE_EDITING 59 60 #define CONFIG_MCFTMR 61 62 #define CONFIG_SYS_LONGHELP 1 63 64 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 65 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 67 68 #define CONFIG_SYS_LOAD_ADDR 0x20000 69 70 #define CONFIG_SYS_MEMTEST_START 0x100000 71 #define CONFIG_SYS_MEMTEST_END 0x400000 72 /*#define CONFIG_SYS_DRAM_TEST 1 */ 73 #undef CONFIG_SYS_DRAM_TEST 74 75 /*----------------------------------------------------------------------* 76 * Clock and PLL Configuration * 77 *----------------------------------------------------------------------*/ 78 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 79 80 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 81 82 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 83 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 84 85 /*----------------------------------------------------------------------* 86 * Network * 87 *----------------------------------------------------------------------*/ 88 89 #define CONFIG_MCFFEC 90 #define CONFIG_MII 1 91 #define CONFIG_MII_INIT 1 92 #define CONFIG_SYS_DISCOVER_PHY 93 #define CONFIG_SYS_RX_ETH_BUFFER 8 94 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 95 96 #define CONFIG_SYS_FEC0_PINMUX 0 97 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 98 #define MCFFEC_TOUT_LOOP 50000 99 100 #define CONFIG_OVERWRITE_ETHADDR_ONCE 101 102 /*------------------------------------------------------------------------- 103 * Low Level Configuration Settings 104 * (address mappings, register initial values, etc.) 105 * You should know what you are doing if you make changes here. 106 *-----------------------------------------------------------------------*/ 107 108 #define CONFIG_SYS_MBAR 0x40000000 109 110 /*----------------------------------------------------------------------- 111 * Definitions for initial stack pointer and data area (in DPRAM) 112 *-----------------------------------------------------------------------*/ 113 114 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 115 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 116 #define CONFIG_SYS_GBL_DATA_OFFSET \ 117 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 118 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 119 120 /*----------------------------------------------------------------------- 121 * Start addresses for the final memory configuration 122 * (Set up by the startup code) 123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 124 */ 125 #define CONFIG_SYS_SDRAM_BASE0 0x00000000 126 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 127 128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 129 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 130 131 #define CONFIG_SYS_MONITOR_LEN 0x20000 132 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 133 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 134 135 /* 136 * For booting Linux, the board info and command line data 137 * have to be in the first 8 MB of memory, since this is 138 * the maximum mapped by the Linux kernel during initialization ?? 139 */ 140 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 141 142 /*----------------------------------------------------------------------- 143 * FLASH organization 144 */ 145 #define CONFIG_FLASH_SHOW_PROGRESS 45 146 147 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 148 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 149 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 150 151 #define CONFIG_SYS_MAX_FLASH_SECT 128 152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 153 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 154 #define CONFIG_SYS_FLASH_PROTECTION 155 156 #define CONFIG_SYS_FLASH_CFI 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 159 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 160 161 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 162 163 /*----------------------------------------------------------------------- 164 * Cache Configuration 165 */ 166 #define CONFIG_SYS_CACHELINE_SIZE 16 167 168 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 169 CONFIG_SYS_INIT_RAM_SIZE - 8) 170 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - 4) 172 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 173 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 174 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 175 CF_ACR_EN | CF_ACR_SM_ALL) 176 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 177 CF_CACR_CEIB | CF_CACR_DBWE | \ 178 CF_CACR_EUSP) 179 180 /*----------------------------------------------------------------------- 181 * Memory bank definitions 182 */ 183 184 #define CONFIG_SYS_CS0_BASE 0xFF000000 185 #define CONFIG_SYS_CS0_CTRL 0x00001980 186 #define CONFIG_SYS_CS0_MASK 0x00FF0001 187 188 #define CONFIG_SYS_CS2_BASE 0xE0000000 189 #define CONFIG_SYS_CS2_CTRL 0x00001980 190 #define CONFIG_SYS_CS2_MASK 0x000F0001 191 192 #define CONFIG_SYS_CS3_BASE 0xE0100000 193 #define CONFIG_SYS_CS3_CTRL 0x00001980 194 #define CONFIG_SYS_CS3_MASK 0x000F0001 195 196 /*----------------------------------------------------------------------- 197 * Port configuration 198 */ 199 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 200 #define CONFIG_SYS_PADDR 0x0000000 201 #define CONFIG_SYS_PADAT 0x0000000 202 203 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 204 #define CONFIG_SYS_PBDDR 0x0000000 205 #define CONFIG_SYS_PBDAT 0x0000000 206 207 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 208 #define CONFIG_SYS_PCDDR 0x0000000 209 #define CONFIG_SYS_PCDAT 0x0000000 210 211 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 212 #define CONFIG_SYS_PCDDR 0x0000000 213 #define CONFIG_SYS_PCDAT 0x0000000 214 215 #define CONFIG_SYS_PASPAR 0x0F0F 216 #define CONFIG_SYS_PEHLPAR 0xC0 217 #define CONFIG_SYS_PUAPAR 0x0F 218 #define CONFIG_SYS_DDRUA 0x05 219 #define CONFIG_SYS_PJPAR 0xFF 220 221 /*----------------------------------------------------------------------- 222 * I2C 223 */ 224 225 #define CONFIG_SYS_I2C 226 #define CONFIG_SYS_I2C_FSL 227 228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 229 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 230 231 #define CONFIG_SYS_FSL_I2C_SPEED 100000 232 #define CONFIG_SYS_FSL_I2C_SLAVE 0 233 234 #ifdef CONFIG_CMD_DATE 235 #define CONFIG_RTC_DS1338 236 #define CONFIG_I2C_RTC_ADDR 0x68 237 #endif 238 239 /*----------------------------------------------------------------------- 240 * VIDEO configuration 241 */ 242 243 #ifdef CONFIG_VIDEO 244 #define CONFIG_VIDEO_VCXK 1 245 246 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 247 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 248 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 249 250 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 251 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 252 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 253 254 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 255 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 256 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 257 258 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 259 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 260 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 261 262 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 263 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 264 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 265 266 #endif /* CONFIG_VIDEO */ 267 #endif /* _CONFIG_M5282EVB_H */ 268 /*---------------------------------------------------------------------*/ 269