xref: /rk3399_rockchip-uboot/include/configs/ds414.h (revision 0a8cc1a3a4206d556da784a0e98598190dfe5408)
1aefb8f4cSPhil Sutter /*
2aefb8f4cSPhil Sutter  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3aefb8f4cSPhil Sutter  *
4aefb8f4cSPhil Sutter  * SPDX-License-Identifier:	GPL-2.0+
5aefb8f4cSPhil Sutter  */
6aefb8f4cSPhil Sutter 
7aefb8f4cSPhil Sutter #ifndef _CONFIG_SYNOLOGY_DS414_H
8aefb8f4cSPhil Sutter #define _CONFIG_SYNOLOGY_DS414_H
9aefb8f4cSPhil Sutter 
10aefb8f4cSPhil Sutter /*
11aefb8f4cSPhil Sutter  * High Level Configuration Options (easy to change)
12aefb8f4cSPhil Sutter  */
13aefb8f4cSPhil Sutter #define CONFIG_DISPLAY_BOARDINFO_LATE
14aefb8f4cSPhil Sutter 
15aefb8f4cSPhil Sutter /*
16aefb8f4cSPhil Sutter  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17aefb8f4cSPhil Sutter  * for DDR ECC byte filling in the SPL before loading the main
18aefb8f4cSPhil Sutter  * U-Boot into it.
19aefb8f4cSPhil Sutter  */
20aefb8f4cSPhil Sutter #define	CONFIG_SYS_TEXT_BASE	0x00800000
21aefb8f4cSPhil Sutter #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
22aefb8f4cSPhil Sutter 
23aefb8f4cSPhil Sutter /*
24aefb8f4cSPhil Sutter  * Commands configuration
25aefb8f4cSPhil Sutter  */
26aefb8f4cSPhil Sutter #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
27aefb8f4cSPhil Sutter #define CONFIG_CMD_ENV
28aefb8f4cSPhil Sutter 
29aefb8f4cSPhil Sutter /* I2C */
30aefb8f4cSPhil Sutter #define CONFIG_SYS_I2C
31aefb8f4cSPhil Sutter #define CONFIG_SYS_I2C_MVTWSI
32aefb8f4cSPhil Sutter #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
33aefb8f4cSPhil Sutter #define CONFIG_SYS_I2C_SLAVE		0x0
34aefb8f4cSPhil Sutter #define CONFIG_SYS_I2C_SPEED		100000
35aefb8f4cSPhil Sutter 
36aefb8f4cSPhil Sutter /* SPI NOR flash default params, used by sf commands */
37aefb8f4cSPhil Sutter #define CONFIG_SF_DEFAULT_SPEED		1000000
38aefb8f4cSPhil Sutter #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
39aefb8f4cSPhil Sutter 
40aefb8f4cSPhil Sutter /* Environment in SPI NOR flash */
41aefb8f4cSPhil Sutter #define CONFIG_ENV_IS_IN_SPI_FLASH
42aefb8f4cSPhil Sutter #define CONFIG_ENV_OFFSET		0x7E0000   /* RedBoot config partition in DTS */
43aefb8f4cSPhil Sutter #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
44aefb8f4cSPhil Sutter #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
45aefb8f4cSPhil Sutter 
46aefb8f4cSPhil Sutter #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
47aefb8f4cSPhil Sutter #define CONFIG_PHY_ADDR			{ 0x1, 0x0 }
48aefb8f4cSPhil Sutter #define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
49aefb8f4cSPhil Sutter 
50aefb8f4cSPhil Sutter #define CONFIG_SYS_ALT_MEMTEST
51aefb8f4cSPhil Sutter 
52aefb8f4cSPhil Sutter /* PCIe support */
53aefb8f4cSPhil Sutter #ifndef CONFIG_SPL_BUILD
54aefb8f4cSPhil Sutter #define CONFIG_PCI
55aefb8f4cSPhil Sutter #define CONFIG_CMD_PCI
56aefb8f4cSPhil Sutter #define CONFIG_CMD_PCI_ENUM
57aefb8f4cSPhil Sutter #define CONFIG_PCI_MVEBU
58aefb8f4cSPhil Sutter #define CONFIG_PCI_SCAN_SHOW
59aefb8f4cSPhil Sutter #endif
60aefb8f4cSPhil Sutter 
61aefb8f4cSPhil Sutter /* USB/EHCI/XHCI configuration */
62aefb8f4cSPhil Sutter 
63aefb8f4cSPhil Sutter #define CONFIG_DM_USB
64aefb8f4cSPhil Sutter #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
65aefb8f4cSPhil Sutter 
66aefb8f4cSPhil Sutter /* FIXME: broken XHCI support
67aefb8f4cSPhil Sutter  * Below defines should enable support for the two rear USB3 ports. Sadly, this
68aefb8f4cSPhil Sutter  * does not work because:
69aefb8f4cSPhil Sutter  * - xhci-pci seems to not support DM_USB, so with that enabled it is not
70aefb8f4cSPhil Sutter  *   found.
71aefb8f4cSPhil Sutter  * - USB init fails, controller does not respond in time */
72aefb8f4cSPhil Sutter #if 0
73aefb8f4cSPhil Sutter #undef CONFIG_DM_USB
74aefb8f4cSPhil Sutter #define CONFIG_USB_XHCI_PCI
75aefb8f4cSPhil Sutter #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
76aefb8f4cSPhil Sutter #endif
77aefb8f4cSPhil Sutter 
78*0a8cc1a3SMasahiro Yamada #if !defined(CONFIG_USB_XHCI_HCD)
79aefb8f4cSPhil Sutter #define CONFIG_USB_EHCI
80aefb8f4cSPhil Sutter #define CONFIG_USB_EHCI_MARVELL
81aefb8f4cSPhil Sutter #define CONFIG_EHCI_IS_TDI
82aefb8f4cSPhil Sutter #endif
83aefb8f4cSPhil Sutter 
84aefb8f4cSPhil Sutter /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
85aefb8f4cSPhil Sutter #define CONFIG_USB_STORAGE
86aefb8f4cSPhil Sutter #define CONFIG_DOS_PARTITION
87aefb8f4cSPhil Sutter #define CONFIG_ISO_PARTITION
88aefb8f4cSPhil Sutter #define CONFIG_SUPPORT_VFAT
89aefb8f4cSPhil Sutter #define CONFIG_SYS_MVFS
90aefb8f4cSPhil Sutter 
91aefb8f4cSPhil Sutter /*
92aefb8f4cSPhil Sutter  * mv-common.h should be defined after CMD configs since it used them
93aefb8f4cSPhil Sutter  * to enable certain macros
94aefb8f4cSPhil Sutter  */
95aefb8f4cSPhil Sutter #include "mv-common.h"
96aefb8f4cSPhil Sutter 
97aefb8f4cSPhil Sutter /*
98aefb8f4cSPhil Sutter  * Memory layout while starting into the bin_hdr via the
99aefb8f4cSPhil Sutter  * BootROM:
100aefb8f4cSPhil Sutter  *
101aefb8f4cSPhil Sutter  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
102aefb8f4cSPhil Sutter  * 0x4000.4030			bin_hdr start address
103aefb8f4cSPhil Sutter  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
104aefb8f4cSPhil Sutter  * 0x4007.fffc			BootROM stack top
105aefb8f4cSPhil Sutter  *
106aefb8f4cSPhil Sutter  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
107aefb8f4cSPhil Sutter  * L2 cache thus cannot be used.
108aefb8f4cSPhil Sutter  */
109aefb8f4cSPhil Sutter 
110aefb8f4cSPhil Sutter /* SPL */
111aefb8f4cSPhil Sutter /* Defines for SPL */
112aefb8f4cSPhil Sutter #define CONFIG_SPL_FRAMEWORK
113aefb8f4cSPhil Sutter #define CONFIG_SPL_TEXT_BASE		0x40004030
114aefb8f4cSPhil Sutter #define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
115aefb8f4cSPhil Sutter 
116aefb8f4cSPhil Sutter #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
117aefb8f4cSPhil Sutter #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
118aefb8f4cSPhil Sutter 
119aefb8f4cSPhil Sutter #ifdef CONFIG_SPL_BUILD
120aefb8f4cSPhil Sutter #define CONFIG_SYS_MALLOC_SIMPLE
121aefb8f4cSPhil Sutter #endif
122aefb8f4cSPhil Sutter 
123aefb8f4cSPhil Sutter #define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
124aefb8f4cSPhil Sutter #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
125aefb8f4cSPhil Sutter 
126aefb8f4cSPhil Sutter #define CONFIG_SPL_LIBCOMMON_SUPPORT
127aefb8f4cSPhil Sutter #define CONFIG_SPL_LIBGENERIC_SUPPORT
128aefb8f4cSPhil Sutter #define CONFIG_SPL_SERIAL_SUPPORT
129aefb8f4cSPhil Sutter #define CONFIG_SPL_I2C_SUPPORT
130aefb8f4cSPhil Sutter 
131aefb8f4cSPhil Sutter /* SPL related SPI defines */
132aefb8f4cSPhil Sutter #define CONFIG_SPL_SPI_SUPPORT
133aefb8f4cSPhil Sutter #define CONFIG_SPL_SPI_FLASH_SUPPORT
134aefb8f4cSPhil Sutter #define CONFIG_SPL_SPI_LOAD
135aefb8f4cSPhil Sutter #define CONFIG_SPL_SPI_BUS		0
136aefb8f4cSPhil Sutter #define CONFIG_SPL_SPI_CS		0
137aefb8f4cSPhil Sutter #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x24000
138aefb8f4cSPhil Sutter 
139aefb8f4cSPhil Sutter /* DS414 bus width is 32bits */
140aefb8f4cSPhil Sutter #define CONFIG_DDR_32BIT
141aefb8f4cSPhil Sutter 
142aefb8f4cSPhil Sutter /* Use random ethernet address if not configured */
143aefb8f4cSPhil Sutter #define CONFIG_LIB_RAND
144aefb8f4cSPhil Sutter #define CONFIG_NET_RANDOM_ETHADDR
145aefb8f4cSPhil Sutter 
146aefb8f4cSPhil Sutter /* Default Environment */
147aefb8f4cSPhil Sutter #define CONFIG_BOOTCOMMAND	"sf read ${loadaddr} 0xd0000 0x700000; bootm"
148aefb8f4cSPhil Sutter #define CONFIG_BOOTARGS		"console=ttyS0,115200"
149aefb8f4cSPhil Sutter #define CONFIG_LOADADDR		0x80000
150aefb8f4cSPhil Sutter #undef CONFIG_PREBOOT		/* override preboot for USB and SPI flash init */
151aefb8f4cSPhil Sutter #define CONFIG_PREBOOT		"usb start; sf probe"
152aefb8f4cSPhil Sutter 
153aefb8f4cSPhil Sutter #endif /* _CONFIG_SYNOLOGY_DS414_H */
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