1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * (C) Copyright 2009 8 * Frederik Kriewitz <frederik@kriewitz.eu> 9 * 10 * Configuration settings for the DevKit8000 board. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* High Level Configuration Options */ 19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 21 22 /* 23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 24 * 64 bytes before this address should be set aside for u-boot.img's 25 * header. That is 0x800FFFC0--0x80100000 should not be used for any 26 * other needs. 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0x80100000 29 30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 32 33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 35 36 #define CONFIG_NAND 37 38 /* Physical Memory Map */ 39 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 40 41 #include <configs/ti_omap3_common.h> 42 43 /* Display CPU and Board information */ 44 #define CONFIG_DISPLAY_BOARDINFO 1 45 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_REVISION_TAG 1 49 50 /* Size of malloc() pool */ 51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 52 /* Sector */ 53 #undef CONFIG_SYS_MALLOC_LEN 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 55 56 /* Hardware drivers */ 57 /* DM9000 */ 58 #define CONFIG_NET_RETRY_COUNT 20 59 #define CONFIG_DRIVER_DM9000 1 60 #define CONFIG_DM9000_BASE 0x2c000000 61 #define DM9000_IO CONFIG_DM9000_BASE 62 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 63 #define CONFIG_DM9000_USE_16BIT 1 64 #define CONFIG_DM9000_NO_SROM 1 65 #undef CONFIG_DM9000_DEBUG 66 67 /* SPI */ 68 #undef CONFIG_SPI 69 #undef CONFIG_OMAP3_SPI 70 71 /* I2C */ 72 #undef CONFIG_SYS_I2C_OMAP24XX 73 #define CONFIG_SYS_I2C_OMAP34XX 74 75 /* TWL4030 */ 76 #define CONFIG_TWL4030_LED 1 77 78 /* Board NAND Info */ 79 #define MTDIDS_DEFAULT "nand0=nand" 80 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 81 "512k(x-loader)," \ 82 "1920k(u-boot)," \ 83 "128k(u-boot-env)," \ 84 "4m(kernel)," \ 85 "-(fs)" 86 87 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 88 /* to access nand */ 89 #define CONFIG_JFFS2_NAND 90 /* nand device jffs2 lives on */ 91 #define CONFIG_JFFS2_DEV "nand0" 92 /* start of jffs2 partition */ 93 #define CONFIG_JFFS2_PART_OFFSET 0x680000 94 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 95 /* partition */ 96 97 /* commands to include */ 98 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 99 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 100 101 #undef CONFIG_SUPPORT_RAW_INITRD 102 #undef CONFIG_FAT_WRITE 103 104 /* BOOTP/DHCP options */ 105 #define CONFIG_BOOTP_SUBNETMASK 106 #define CONFIG_BOOTP_GATEWAY 107 #define CONFIG_BOOTP_HOSTNAME 108 #define CONFIG_BOOTP_NISDOMAIN 109 #define CONFIG_BOOTP_BOOTPATH 110 #define CONFIG_BOOTP_BOOTFILESIZE 111 #define CONFIG_BOOTP_DNS 112 #define CONFIG_BOOTP_DNS2 113 #define CONFIG_BOOTP_SEND_HOSTNAME 114 #define CONFIG_BOOTP_NTPSERVER 115 #define CONFIG_BOOTP_TIMEOFFSET 116 #undef CONFIG_BOOTP_VENDOREX 117 118 /* Environment information */ 119 #define CONFIG_EXTRA_ENV_SETTINGS \ 120 "loadaddr=0x82000000\0" \ 121 "console=ttyO2,115200n8\0" \ 122 "mmcdev=0\0" \ 123 "vram=12M\0" \ 124 "dvimode=1024x768MR-16@60\0" \ 125 "defaultdisplay=dvi\0" \ 126 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 127 "kernelopts=rw\0" \ 128 "commonargs=" \ 129 "setenv bootargs console=${console} " \ 130 "vram=${vram} " \ 131 "omapfb.mode=dvi:${dvimode} " \ 132 "omapdss.def_disp=${defaultdisplay}\0" \ 133 "mmcargs=" \ 134 "run commonargs; " \ 135 "setenv bootargs ${bootargs} " \ 136 "root=/dev/mmcblk0p2 " \ 137 "rootwait " \ 138 "${kernelopts}\0" \ 139 "nandargs=" \ 140 "run commonargs; " \ 141 "setenv bootargs ${bootargs} " \ 142 "omapfb.mode=dvi:${dvimode} " \ 143 "omapdss.def_disp=${defaultdisplay} " \ 144 "root=/dev/mtdblock4 " \ 145 "rootfstype=jffs2 " \ 146 "${kernelopts}\0" \ 147 "netargs=" \ 148 "run commonargs; " \ 149 "setenv bootargs ${bootargs} " \ 150 "root=/dev/nfs " \ 151 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 152 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 153 "${kernelopts} " \ 154 "dnsip1=${dnsip} " \ 155 "dnsip2=${dnsip2}\0" \ 156 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 157 "bootscript=echo Running bootscript from mmc ...; " \ 158 "source ${loadaddr}\0" \ 159 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 160 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 161 "mmcboot=echo Booting from mmc ...; " \ 162 "run mmcargs; " \ 163 "bootm ${loadaddr}\0" \ 164 "nandboot=echo Booting from nand ...; " \ 165 "run nandargs; " \ 166 "nand read ${loadaddr} 280000 400000; " \ 167 "bootm ${loadaddr}\0" \ 168 "netboot=echo Booting from network ...; " \ 169 "dhcp ${loadaddr}; " \ 170 "run netargs; " \ 171 "bootm ${loadaddr}\0" \ 172 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 173 "if run loadbootscript; then " \ 174 "run bootscript; " \ 175 "else " \ 176 "if run loaduimage; then " \ 177 "run mmcboot; " \ 178 "else run nandboot; " \ 179 "fi; " \ 180 "fi; " \ 181 "else run nandboot; fi\0" 182 183 #define CONFIG_BOOTCOMMAND "run autoboot" 184 185 /* Boot Argument Buffer Size */ 186 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 187 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 188 0x01000000) /* 16MB */ 189 190 /* NAND and environment organization */ 191 #define CONFIG_ENV_IS_IN_NAND 1 192 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 193 194 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 195 196 /* SRAM config */ 197 #define CONFIG_SYS_SRAM_START 0x40200000 198 #define CONFIG_SYS_SRAM_SIZE 0x10000 199 200 /* Defines for SPL */ 201 202 #undef CONFIG_SPL_TEXT_BASE 203 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 204 205 /* NAND boot config */ 206 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 207 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 208 #define CONFIG_SYS_NAND_PAGE_COUNT 64 209 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 210 #define CONFIG_SYS_NAND_OOBSIZE 64 211 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 212 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 213 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 214 10, 11, 12, 13} 215 216 #define CONFIG_SYS_NAND_ECCSIZE 512 217 #define CONFIG_SYS_NAND_ECCBYTES 3 218 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 219 220 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 221 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 222 223 /* SPL OS boot options */ 224 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 225 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 226 0x400000) 227 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 228 229 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 230 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 231 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 232 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 233 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 234 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 235 236 #undef CONFIG_SYS_SPL_ARGS_ADDR 237 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 238 239 #endif /* __CONFIG_H */ 240