xref: /rk3399_rockchip-uboot/include/configs/devkit3250.h (revision 78d1e1d0a157c8b48ea19be6170b992745d30f38)
1 /*
2  * Embest/Timll DevKit3250 board configuration file
3  *
4  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_DEVKIT3250_H__
10 #define __CONFIG_DEVKIT3250_H__
11 
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
15 
16 /*
17  * Define DevKit3250 machine type by hand until it lands in mach-types
18  */
19 #define MACH_TYPE_DEVKIT3250		3697
20 #define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250
21 
22 #define CONFIG_SYS_ICACHE_OFF
23 #define CONFIG_SYS_DCACHE_OFF
24 #if !defined(CONFIG_SPL_BUILD)
25 #define CONFIG_SKIP_LOWLEVEL_INIT
26 #endif
27 #define CONFIG_BOARD_EARLY_INIT_F
28 
29 /*
30  * Memory configurations
31  */
32 #define CONFIG_NR_DRAM_BANKS		1
33 #define CONFIG_SYS_MALLOC_LEN		SZ_1M
34 #define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
35 #define CONFIG_SYS_SDRAM_SIZE		SZ_64M
36 #define CONFIG_SYS_TEXT_BASE		0x83F00000
37 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
38 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
39 
40 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
41 
42 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
43 					 - GENERATED_GBL_DATA_SIZE)
44 
45 /*
46  * Serial Driver
47  */
48 #define CONFIG_SYS_LPC32XX_UART		5   /* UART5 */
49 #define CONFIG_BAUDRATE			115200
50 
51 /*
52  * DMA
53  */
54 #if !defined(CONFIG_SPL_BUILD)
55 #define CONFIG_DMA_LPC32XX
56 #endif
57 
58 /*
59  * I2C
60  */
61 #define CONFIG_SYS_I2C
62 #define CONFIG_SYS_I2C_LPC32XX
63 #define CONFIG_SYS_I2C_SPEED		100000
64 
65 /*
66  * GPIO
67  */
68 #define CONFIG_LPC32XX_GPIO
69 
70 /*
71  * SSP/SPI
72  */
73 #define CONFIG_LPC32XX_SSP
74 #define CONFIG_LPC32XX_SSP_TIMEOUT	100000
75 
76 /*
77  * Ethernet
78  */
79 #define CONFIG_RMII
80 #define CONFIG_PHY_SMSC
81 #define CONFIG_LPC32XX_ETH
82 #define CONFIG_PHYLIB
83 #define CONFIG_PHY_ADDR			0x1F
84 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
85 #define CONFIG_CMD_MII
86 
87 /*
88  * NOR Flash
89  */
90 #define CONFIG_SYS_MAX_FLASH_BANKS	1
91 #define CONFIG_SYS_MAX_FLASH_SECT	71
92 #define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
93 #define CONFIG_SYS_FLASH_SIZE		SZ_4M
94 #define CONFIG_SYS_FLASH_CFI
95 
96 /*
97  * NAND controller
98  */
99 #define CONFIG_NAND_LPC32XX_SLC
100 #define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
101 #define CONFIG_SYS_MAX_NAND_DEVICE	1
102 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
103 
104 /*
105  * NAND chip timings
106  */
107 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS	14
108 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH		66666666
109 #define CONFIG_LPC32XX_NAND_SLC_WHOLD		200000000
110 #define CONFIG_LPC32XX_NAND_SLC_WSETUP		50000000
111 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS	14
112 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH		66666666
113 #define CONFIG_LPC32XX_NAND_SLC_RHOLD		200000000
114 #define CONFIG_LPC32XX_NAND_SLC_RSETUP		50000000
115 
116 #define CONFIG_SYS_NAND_BLOCK_SIZE		0x20000
117 #define CONFIG_SYS_NAND_PAGE_SIZE		NAND_LARGE_BLOCK_PAGE_SIZE
118 #define CONFIG_SYS_NAND_USE_FLASH_BBT
119 
120 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_NAND
122 
123 /*
124  * USB
125  */
126 #define CONFIG_USB_OHCI_LPC32XX
127 #define CONFIG_USB_ISP1301_I2C_ADDR		0x2d
128 #define CONFIG_USB_STORAGE
129 #define CONFIG_CMD_FAT
130 
131 /*
132  * U-Boot General Configurations
133  */
134 #define CONFIG_SYS_LONGHELP
135 #define CONFIG_SYS_CBSIZE		1024
136 #define CONFIG_SYS_PBSIZE		\
137 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
138 #define CONFIG_SYS_MAXARGS		16
139 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
140 
141 #define CONFIG_AUTO_COMPLETE
142 #define CONFIG_CMDLINE_EDITING
143 #define CONFIG_VERSION_VARIABLE
144 #define CONFIG_DISPLAY_CPUINFO
145 #define CONFIG_DOS_PARTITION
146 
147 /*
148  * Pass open firmware flat tree
149  */
150 
151 /*
152  * Environment
153  */
154 #define CONFIG_ENV_IS_IN_NAND		1
155 #define CONFIG_ENV_SIZE			SZ_128K
156 #define CONFIG_ENV_OFFSET		0x000A0000
157 
158 #define CONFIG_BOOTCOMMAND			\
159 	"dhcp; "				\
160 	"tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "		\
161 	"tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "	\
162 	"setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "	\
163 	"setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "			\
164 	"bootm ${loadaddr} - ${dtbaddr}"
165 
166 #define CONFIG_EXTRA_ENV_SETTINGS		\
167 	"autoload=no\0"				\
168 	"ethaddr=00:01:90:00:C0:81\0"		\
169 	"dtbaddr=0x81000000\0"			\
170 	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"	\
171 	"tftpdir=vladimir/oe/devkit3250\0"	\
172 	"userargs=oops=panic\0"
173 
174 /*
175  * U-Boot Commands
176  */
177 #define CONFIG_CMD_CACHE
178 
179 /*
180  * Boot Linux
181  */
182 #define CONFIG_CMDLINE_TAG
183 #define CONFIG_SETUP_MEMORY_TAGS
184 #define CONFIG_ZERO_BOOTDELAY_CHECK
185 #define CONFIG_BOOTDELAY		1
186 
187 #define CONFIG_BOOTFILE			"uImage"
188 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
189 #define CONFIG_LOADADDR			0x80008000
190 
191 /*
192  * SPL specific defines
193  */
194 /* SPL will be executed at offset 0 */
195 #define CONFIG_SPL_TEXT_BASE		0x00000000
196 
197 /* SPL will use SRAM as stack */
198 #define CONFIG_SPL_STACK		0x0000FFF8
199 #define CONFIG_SPL_BOARD_INIT
200 
201 /* Use the framework and generic lib */
202 #define CONFIG_SPL_FRAMEWORK
203 #define CONFIG_SPL_LIBGENERIC_SUPPORT
204 #define CONFIG_SPL_LIBCOMMON_SUPPORT
205 
206 /* SPL will use serial */
207 #define CONFIG_SPL_SERIAL_SUPPORT
208 
209 /* SPL loads an image from NAND */
210 #define CONFIG_SPL_NAND_SIMPLE
211 #define CONFIG_SPL_NAND_RAW_ONLY
212 #define CONFIG_SPL_NAND_SUPPORT
213 #define CONFIG_SPL_NAND_DRIVERS
214 
215 #define CONFIG_SPL_NAND_ECC
216 #define CONFIG_SPL_NAND_SOFTECC
217 
218 #define CONFIG_SPL_MAX_SIZE		0x20000
219 #define CONFIG_SPL_PAD_TO		CONFIG_SPL_MAX_SIZE
220 
221 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
222 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
223 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
224 
225 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
226 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
227 
228 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
229 #define CONFIG_SYS_MONITOR_LEN		CONFIG_SYS_NAND_U_BOOT_SIZE
230 
231 /*
232  * Include SoC specific configuration
233  */
234 #include <asm/arch/config.h>
235 
236 #endif  /* __CONFIG_DEVKIT3250_H__*/
237