1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #ifdef CONFIG_DBAU1000 19 /* Also known as Merlot */ 20 #define CONFIG_SOC_AU1000 1 21 #else 22 #ifdef CONFIG_DBAU1100 23 #define CONFIG_SOC_AU1100 1 24 #else 25 #ifdef CONFIG_DBAU1500 26 #define CONFIG_SOC_AU1500 1 27 #else 28 #ifdef CONFIG_DBAU1550 29 /* Cabernet */ 30 #define CONFIG_SOC_AU1550 1 31 #else 32 #error "No valid board set" 33 #endif 34 #endif 35 #endif 36 #endif 37 38 /* valid baudrates */ 39 40 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 41 #undef CONFIG_BOOTARGS 42 43 #define CONFIG_EXTRA_ENV_SETTINGS \ 44 "addmisc=setenv bootargs ${bootargs} " \ 45 "console=ttyS0,${baudrate} " \ 46 "panic=1\0" \ 47 "bootfile=/tftpboot/vmlinux.srec\0" \ 48 "load=tftp 80500000 ${u-boot}\0" \ 49 "" 50 51 #ifdef CONFIG_DBAU1550 52 /* Boot from flash by default, revert to bootp */ 53 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 54 #else /* CONFIG_DBAU1550 */ 55 #define CONFIG_BOOTCOMMAND "bootp;bootm" 56 #endif /* CONFIG_DBAU1550 */ 57 58 /* 59 * BOOTP options 60 */ 61 #define CONFIG_BOOTP_BOOTFILESIZE 62 #define CONFIG_BOOTP_BOOTPATH 63 #define CONFIG_BOOTP_GATEWAY 64 #define CONFIG_BOOTP_HOSTNAME 65 66 /* 67 * Command line configuration. 68 */ 69 #undef CONFIG_CMD_BEDBUG 70 71 #ifdef CONFIG_DBAU1550 72 73 #undef CONFIG_CMD_IDE 74 #undef CONFIG_CMD_PCMCIA 75 76 #else 77 78 #define CONFIG_CMD_IDE 79 80 #endif 81 82 /* 83 * Miscellaneous configurable options 84 */ 85 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 86 87 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 88 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 89 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 90 91 #define CONFIG_SYS_MALLOC_LEN 128*1024 92 93 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 94 95 #define CONFIG_SYS_MHZ 396 96 97 #if (CONFIG_SYS_MHZ % 12) != 0 98 #error "Invalid CPU frequency - must be multiple of 12!" 99 #endif 100 101 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 102 103 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 104 105 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 106 107 #define CONFIG_SYS_MEMTEST_START 0x80100000 108 #define CONFIG_SYS_MEMTEST_END 0x80800000 109 110 /*----------------------------------------------------------------------- 111 * FLASH and environment organization 112 */ 113 #ifdef CONFIG_DBAU1550 114 115 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 116 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 117 118 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 119 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 120 121 #else /* CONFIG_DBAU1550 */ 122 123 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 124 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 125 126 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 127 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 128 129 #endif /* CONFIG_DBAU1550 */ 130 131 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 132 133 #define CONFIG_SYS_FLASH_CFI 1 134 #define CONFIG_FLASH_CFI_DRIVER 1 135 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 137 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 138 139 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 140 141 /* We boot from this flash, selected with dip switch */ 142 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 143 144 /* timeout values are in ticks */ 145 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 146 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 147 148 #define CONFIG_ENV_IS_NOWHERE 1 149 150 /* Address and size of Primary Environment Sector */ 151 #define CONFIG_ENV_ADDR 0xB0030000 152 #define CONFIG_ENV_SIZE 0x10000 153 154 #define CONFIG_FLASH_16BIT 155 156 #define CONFIG_NR_DRAM_BANKS 2 157 158 #ifdef CONFIG_DBAU1550 159 #define MEM_SIZE 192 160 #else 161 #define MEM_SIZE 64 162 #endif 163 164 #define CONFIG_MEMSIZE_IN_BYTES 165 166 #ifndef CONFIG_DBAU1550 167 /*---ATA PCMCIA ------------------------------------*/ 168 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 169 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 170 #define CONFIG_PCMCIA_SLOT_A 171 172 #define CONFIG_ATAPI 1 173 174 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 175 #define CONFIG_IDE_PCMCIA 1 176 177 /* We only support one slot for now */ 178 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 179 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 180 181 #undef CONFIG_IDE_LED /* LED for ide not supported */ 182 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 183 184 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 185 186 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 187 188 /* Offset for data I/O */ 189 #define CONFIG_SYS_ATA_DATA_OFFSET 8 190 191 /* Offset for normal register accesses */ 192 #define CONFIG_SYS_ATA_REG_OFFSET 0 193 194 /* Offset for alternate registers */ 195 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 196 #endif /* CONFIG_DBAU1550 */ 197 198 #endif /* __CONFIG_H */ 199