1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #ifdef CONFIG_DBAU1000 21 /* Also known as Merlot */ 22 #define CONFIG_SOC_AU1000 1 23 #else 24 #ifdef CONFIG_DBAU1100 25 #define CONFIG_SOC_AU1100 1 26 #else 27 #ifdef CONFIG_DBAU1500 28 #define CONFIG_SOC_AU1500 1 29 #else 30 #ifdef CONFIG_DBAU1550 31 /* Cabernet */ 32 #define CONFIG_SOC_AU1550 1 33 #else 34 #error "No valid board set" 35 #endif 36 #endif 37 #endif 38 #endif 39 40 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 41 42 #define CONFIG_BAUDRATE 115200 43 44 /* valid baudrates */ 45 46 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 47 #undef CONFIG_BOOTARGS 48 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 "addmisc=setenv bootargs ${bootargs} " \ 51 "console=ttyS0,${baudrate} " \ 52 "panic=1\0" \ 53 "bootfile=/tftpboot/vmlinux.srec\0" \ 54 "load=tftp 80500000 ${u-boot}\0" \ 55 "" 56 57 #ifdef CONFIG_DBAU1550 58 /* Boot from flash by default, revert to bootp */ 59 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 60 #else /* CONFIG_DBAU1550 */ 61 #define CONFIG_BOOTCOMMAND "bootp;bootm" 62 #endif /* CONFIG_DBAU1550 */ 63 64 /* 65 * BOOTP options 66 */ 67 #define CONFIG_BOOTP_BOOTFILESIZE 68 #define CONFIG_BOOTP_BOOTPATH 69 #define CONFIG_BOOTP_GATEWAY 70 #define CONFIG_BOOTP_HOSTNAME 71 72 /* 73 * Command line configuration. 74 */ 75 #undef CONFIG_CMD_BEDBUG 76 77 #ifdef CONFIG_DBAU1550 78 79 #undef CONFIG_CMD_IDE 80 #undef CONFIG_CMD_PCMCIA 81 82 #else 83 84 #define CONFIG_CMD_IDE 85 86 #endif 87 88 /* 89 * Miscellaneous configurable options 90 */ 91 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 92 93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 94 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 95 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 96 97 #define CONFIG_SYS_MALLOC_LEN 128*1024 98 99 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 100 101 #define CONFIG_SYS_MHZ 396 102 103 #if (CONFIG_SYS_MHZ % 12) != 0 104 #error "Invalid CPU frequency - must be multiple of 12!" 105 #endif 106 107 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 108 109 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 110 111 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 112 113 #define CONFIG_SYS_MEMTEST_START 0x80100000 114 #define CONFIG_SYS_MEMTEST_END 0x80800000 115 116 /*----------------------------------------------------------------------- 117 * FLASH and environment organization 118 */ 119 #ifdef CONFIG_DBAU1550 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 123 124 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 125 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 126 127 #else /* CONFIG_DBAU1550 */ 128 129 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 130 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 131 132 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 133 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 134 135 #endif /* CONFIG_DBAU1550 */ 136 137 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 138 139 #define CONFIG_SYS_FLASH_CFI 1 140 #define CONFIG_FLASH_CFI_DRIVER 1 141 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 143 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 144 145 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 146 147 /* We boot from this flash, selected with dip switch */ 148 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 149 150 /* timeout values are in ticks */ 151 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 152 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 153 154 #define CONFIG_ENV_IS_NOWHERE 1 155 156 /* Address and size of Primary Environment Sector */ 157 #define CONFIG_ENV_ADDR 0xB0030000 158 #define CONFIG_ENV_SIZE 0x10000 159 160 #define CONFIG_FLASH_16BIT 161 162 #define CONFIG_NR_DRAM_BANKS 2 163 164 #ifdef CONFIG_DBAU1550 165 #define MEM_SIZE 192 166 #else 167 #define MEM_SIZE 64 168 #endif 169 170 #define CONFIG_MEMSIZE_IN_BYTES 171 172 #ifndef CONFIG_DBAU1550 173 /*---ATA PCMCIA ------------------------------------*/ 174 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 175 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 176 #define CONFIG_PCMCIA_SLOT_A 177 178 #define CONFIG_ATAPI 1 179 #define CONFIG_MAC_PARTITION 1 180 181 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 182 #define CONFIG_IDE_PCMCIA 1 183 184 /* We only support one slot for now */ 185 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 186 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 187 188 #undef CONFIG_IDE_LED /* LED for ide not supported */ 189 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 190 191 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 192 193 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 194 195 /* Offset for data I/O */ 196 #define CONFIG_SYS_ATA_DATA_OFFSET 8 197 198 /* Offset for normal register accesses */ 199 #define CONFIG_SYS_ATA_REG_OFFSET 0 200 201 /* Offset for alternate registers */ 202 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 203 #endif /* CONFIG_DBAU1550 */ 204 205 /*----------------------------------------------------------------------- 206 * Cache Configuration 207 */ 208 #define CONFIG_SYS_DCACHE_SIZE 16384 209 #define CONFIG_SYS_ICACHE_SIZE 16384 210 #define CONFIG_SYS_CACHELINE_SIZE 32 211 212 #endif /* __CONFIG_H */ 213