1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #ifdef CONFIG_DBAU1000 21 /* Also known as Merlot */ 22 #define CONFIG_SOC_AU1000 1 23 #else 24 #ifdef CONFIG_DBAU1100 25 #define CONFIG_SOC_AU1100 1 26 #else 27 #ifdef CONFIG_DBAU1500 28 #define CONFIG_SOC_AU1500 1 29 #else 30 #ifdef CONFIG_DBAU1550 31 /* Cabernet */ 32 #define CONFIG_SOC_AU1550 1 33 #else 34 #error "No valid board set" 35 #endif 36 #endif 37 #endif 38 #endif 39 40 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 41 42 #define CONFIG_BAUDRATE 115200 43 44 /* valid baudrates */ 45 46 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 47 #undef CONFIG_BOOTARGS 48 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 "addmisc=setenv bootargs ${bootargs} " \ 51 "console=ttyS0,${baudrate} " \ 52 "panic=1\0" \ 53 "bootfile=/tftpboot/vmlinux.srec\0" \ 54 "load=tftp 80500000 ${u-boot}\0" \ 55 "" 56 57 #ifdef CONFIG_DBAU1550 58 /* Boot from flash by default, revert to bootp */ 59 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 60 #else /* CONFIG_DBAU1550 */ 61 #define CONFIG_BOOTCOMMAND "bootp;bootm" 62 #endif /* CONFIG_DBAU1550 */ 63 64 65 /* 66 * BOOTP options 67 */ 68 #define CONFIG_BOOTP_BOOTFILESIZE 69 #define CONFIG_BOOTP_BOOTPATH 70 #define CONFIG_BOOTP_GATEWAY 71 #define CONFIG_BOOTP_HOSTNAME 72 73 74 /* 75 * Command line configuration. 76 */ 77 #include <config_cmd_default.h> 78 79 #undef CONFIG_CMD_BDI 80 #undef CONFIG_CMD_BEDBUG 81 #undef CONFIG_CMD_ELF 82 #undef CONFIG_CMD_SAVEENV 83 #undef CONFIG_CMD_FAT 84 #undef CONFIG_CMD_FPGA 85 #undef CONFIG_CMD_MII 86 #undef CONFIG_CMD_RUN 87 88 89 #ifdef CONFIG_DBAU1550 90 91 #define CONFIG_CMD_FLASH 92 #define CONFIG_CMD_LOADB 93 94 #undef CONFIG_CMD_I2C 95 #undef CONFIG_CMD_IDE 96 #undef CONFIG_CMD_NFS 97 #undef CONFIG_CMD_PCMCIA 98 99 #else 100 101 #define CONFIG_CMD_IDE 102 #define CONFIG_CMD_DHCP 103 104 #undef CONFIG_CMD_FLASH 105 #undef CONFIG_CMD_LOADB 106 #undef CONFIG_CMD_LOADS 107 108 #endif 109 110 111 /* 112 * Miscellaneous configurable options 113 */ 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 115 116 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ 117 118 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 120 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 121 122 #define CONFIG_SYS_MALLOC_LEN 128*1024 123 124 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 125 126 #define CONFIG_SYS_MHZ 396 127 128 #if (CONFIG_SYS_MHZ % 12) != 0 129 #error "Invalid CPU frequency - must be multiple of 12!" 130 #endif 131 132 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 133 134 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 135 136 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 137 138 #define CONFIG_SYS_MEMTEST_START 0x80100000 139 #define CONFIG_SYS_MEMTEST_END 0x80800000 140 141 /*----------------------------------------------------------------------- 142 * FLASH and environment organization 143 */ 144 #ifdef CONFIG_DBAU1550 145 146 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 148 149 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 150 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 151 152 #else /* CONFIG_DBAU1550 */ 153 154 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 156 157 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 158 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 159 160 #endif /* CONFIG_DBAU1550 */ 161 162 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 163 164 #define CONFIG_SYS_FLASH_CFI 1 165 #define CONFIG_FLASH_CFI_DRIVER 1 166 167 /* The following #defines are needed to get flash environment right */ 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 169 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 170 171 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 172 173 /* We boot from this flash, selected with dip switch */ 174 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 175 176 /* timeout values are in ticks */ 177 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 178 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 179 180 #define CONFIG_ENV_IS_NOWHERE 1 181 182 /* Address and size of Primary Environment Sector */ 183 #define CONFIG_ENV_ADDR 0xB0030000 184 #define CONFIG_ENV_SIZE 0x10000 185 186 #define CONFIG_FLASH_16BIT 187 188 #define CONFIG_NR_DRAM_BANKS 2 189 190 191 #ifdef CONFIG_DBAU1550 192 #define MEM_SIZE 192 193 #else 194 #define MEM_SIZE 64 195 #endif 196 197 #define CONFIG_MEMSIZE_IN_BYTES 198 199 #ifndef CONFIG_DBAU1550 200 /*---ATA PCMCIA ------------------------------------*/ 201 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 202 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 203 #define CONFIG_PCMCIA_SLOT_A 204 205 #define CONFIG_ATAPI 1 206 #define CONFIG_MAC_PARTITION 1 207 208 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 209 #define CONFIG_IDE_PCMCIA 1 210 211 /* We only support one slot for now */ 212 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 213 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 214 215 #undef CONFIG_IDE_LED /* LED for ide not supported */ 216 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 217 218 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 219 220 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 221 222 /* Offset for data I/O */ 223 #define CONFIG_SYS_ATA_DATA_OFFSET 8 224 225 /* Offset for normal register accesses */ 226 #define CONFIG_SYS_ATA_REG_OFFSET 0 227 228 /* Offset for alternate registers */ 229 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 230 #endif /* CONFIG_DBAU1550 */ 231 232 /*----------------------------------------------------------------------- 233 * Cache Configuration 234 */ 235 #define CONFIG_SYS_DCACHE_SIZE 16384 236 #define CONFIG_SYS_ICACHE_SIZE 16384 237 #define CONFIG_SYS_CACHELINE_SIZE 32 238 239 #endif /* __CONFIG_H */ 240